GPU/Shader Instruction Set: Difference between revisions
fixed MAD SRC order |
i0-i7 used for LOOP |
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| Line 93: | Line 93: | ||
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Format 3 : (used for conditional flow control instructions) | Format 3 : (used for uniform-based conditional flow control instructions) | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
|- | |- | ||
| Line 110: | Line 110: | ||
| 0x16 | | 0x16 | ||
| 0x4 | | 0x4 | ||
| Uniform | | Uniform ID (BOOL/INT) | ||
|- | |- | ||
| 0x1A | | 0x1A | ||
| Line 245: | Line 245: | ||
| 0x23 | | 0x23 | ||
| 1 | | 1 | ||
| BREAK | | BREAK | ||
| Conditionally breaks out of LOOP block | | Conditionally breaks out of LOOP block. Conditions for this are assumed to work the same was as for IF. | ||
|- | |- | ||
| 0x24 | | 0x24 | ||
| Line 270: | Line 270: | ||
| 0x29 | | 0x29 | ||
| 3 | | 3 | ||
| | | FORLOOP | ||
| Loops over the code between itself and DST | | Loops over the code between itself and DST. Increments lcnt after each loop. Stops looping once lcnt reaches the value contained by the integer uniform specified by INT. (i0-i7) | ||
|- | |- | ||
| 0x2A | | 0x2A | ||
| Line 395: | Line 395: | ||
== Registers == | == Registers == | ||
Most registers (all the ones within the 0x00-0x7F range) are float[4] vectors. There are also boolean registers (b0-b7) and integer registers (i0-i7). How the latter ones are set is as of yet unknown. | |||
Attribute (input, RO) registers are located within the 0x0-0xF range. What data they are fed is specified by the CPU. | Attribute (input, RO) registers are located within the 0x0-0xF range. What data they are fed is specified by the CPU. | ||