NDMA Registers: Difference between revisions
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== Registers == | == Registers == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! | ! Old3DS | ||
! | ! Name | ||
! | ! Address | ||
! Width | |||
! Used by | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_GLOBAL_CNT|NDMA_GLOBAL_CNT]] | |||
| 0x10002000 | | 0x10002000 | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_SRC_ADDR|NDMA_SRC_ADDR]](n) | |||
| 0x10002004 + (n*0x1c) | | 0x10002004 + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_DST_ADDR|NDMA_DST_ADDR]](n) | |||
| 0x10002008 + (n*0x1c) | | 0x10002008 + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_TRANSFER_CNT|NDMA_TRANSFER_CNT]](n) | |||
| 0x1000200c + (n*0x1c) | | 0x1000200c + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_WRITE_CNT|NDMA_WRITE_CNT]](n) | |||
| 0x10002010 + (n*0x1c) | | 0x10002010 + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_BLOCK_CNT|NDMA_BLOCK_CNT]](n) | |||
| 0x10002014 + (n*0x1c) | | 0x10002014 + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_FILL_DATA|NDMA_FILL_DATA]](n) | |||
| 0x10002018 + (n*0x1c) | | 0x10002018 + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|- | |- | ||
| | | style="background: green" | Yes | ||
| [[#NDMA_CNT|NDMA_CNT]](n) | |||
| 0x1000201C + (n*0x1c) | | 0x1000201C + (n*0x1c) | ||
| 4 | | 4 | ||
| | |||
|} | |} | ||
== | == NDMA_GLOBAL_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
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|} | |} | ||
== | == NDMA_SRC_ADDR == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
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| Source data address. Must be multiple of 4. | | Source data address. Must be multiple of 4. | ||
|} | |} | ||
Like old DMA, | Like old DMA, NDMA_SRC_ADDR is copied to internal registers when written to. | ||
== | == NDMA_DST_ADDR == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
| Line 70: | Line 88: | ||
| Destination data address. Must be multiple of 4. | | Destination data address. Must be multiple of 4. | ||
|} | |} | ||
Like old DMA, | Like old DMA, NDMA_DST_ADDR is copied to internal registers when written to. | ||
== | == NDMA_TRANSFER_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
| Line 81: | Line 99: | ||
|} | |} | ||
== | == NDMA_WRITE_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
| Line 90: | Line 108: | ||
|} | |} | ||
== | == NDMA_BLOCK_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
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|} | |} | ||
== | == NDMA_FILL_DATA == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
| Line 111: | Line 129: | ||
|} | |} | ||
== | == NDMA_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! BIT | ! BIT | ||
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== Block transfers == | == Block transfers == | ||
First, a word is always 32 bits. Second, the block transfer specified in | First, a word is always 32 bits. Second, the block transfer specified in NDMA_CNT is the smallest atom of data that will be transferred in a burst. The bus is monopolized until this block is transferred, without splitting up. | ||
The next block transfer will happen after the specified time in the | The next block transfer will happen after the specified time in the NDMA_BLOCK_CNT interval timer, until done. | ||
== Immediate mode == | == Immediate mode == | ||
Transfers the words specified in | Transfers the words specified in NDMA_WRITE_CNT immediately following block transfer rules. NDMA_TRANSFER_CNT and repeating mode are ignored. | ||
== Repeating mode == | == Repeating mode == | ||
Transfers the words specified in | Transfers the words specified in NDMA_WRITE_CNT following the startup mode event. NDMA_TRANSFER_CNT is ignored. | ||
== No immediate and no repeating mode == | == No immediate and no repeating mode == | ||
Transfers the words specified in | Transfers the words specified in NDMA_WRITE_CNT for each startup event, and gets disabled when the total number of words in NDMA_TRANSFER_CNT are transferred. | ||