SPI Registers: Difference between revisions
No edit summary |
No edit summary |
||
| Line 17: | Line 17: | ||
| 0x10142002 | | 0x10142002 | ||
| 1 | | 1 | ||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]0 | |||
| 0x10142800 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| SPI_NEW_???0 | |||
| 0x10142804 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]0 | |||
| 0x10142808 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]0 | |||
| 0x1014280C | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]0 | |||
| 0x101428010 | |||
| 4 | |||
| | | | ||
|- | |- | ||
| Line 29: | Line 59: | ||
| 0x10143002 | | 0x10143002 | ||
| 1 | | 1 | ||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]1 | |||
| 0x10143800 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| SPI_NEW_???1 | |||
| 0x10143804 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]1 | |||
| 0x10143808 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]1 | |||
| 0x1014380C | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]1 | |||
| 0x101438010 | |||
| 4 | |||
| | | | ||
|- | |- | ||
| Line 41: | Line 101: | ||
| 0x10160002 | | 0x10160002 | ||
| 1 | | 1 | ||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]2 | |||
| 0x10160800 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| SPI_NEW_???2 | |||
| 0x10160804 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]2 | |||
| 0x10160808 | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]2 | |||
| 0x1016080C | |||
| 4 | |||
| | |||
|- | |||
| style="background: green" | Yes | |||
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]2 | |||
| 0x101608010 | |||
| 4 | |||
| | | | ||
|} | |} | ||
== SPI_CNT == | == SPI_CNT == | ||
This is the old NDS/DSi SPI interface. | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Old3DS | ! Old3DS | ||
| Line 76: | Line 168: | ||
| SPI Bus Enable (0=Disable, 1=Enable) | | SPI Bus Enable (0=Disable, 1=Enable) | ||
|} | |} | ||
== SPI_NEW_CNT == | |||
This is an alternative faster interface introduced with the 3DS. | |||
{| class="wikitable" border="1" | |||
! Old3DS | |||
! Name | |||
|- | |||
| 6-7 | |||
| Device Select | |||
|- | |||
| 13 | |||
| Transfer Direction? (0=Incoming, 1=Outgoing) | |||
|- | |||
| 15 | |||
| Busy/enable | |||
|} | |||
==SPI_NEW_BLKLEN== | |||
The number of bytes to be sent/read is written to this register. | |||
==SPI_NEW_FIFO== | |||
32-bit FIFO for reading/writing the SPI payload. | |||
==SPI_NEW_STATUS== | |||
Bit0: FIFO busy. | |||