AES Registers: Difference between revisions
m →Keyslots: Formatted keyslots 0x18, 0x1B, 0x25, 0x2C the same way. |
WulfyStylez (talk | contribs) |
||
| Line 194: | Line 194: | ||
This register specifies the counter (CTR mode), nonce (CCM mode) or the initialization vector (CBC mode) depending on the mode of operation. | This register specifies the counter (CTR mode), nonce (CCM mode) or the initialization vector (CBC mode) depending on the mode of operation. | ||
For CBC and CTR mode this register takes up the full 16 bytes, but for CCM mode the nonce is only the first 12 bytes. | For CBC and CTR mode this register takes up the full 16 bytes, but for CCM mode the nonce is only the first 12 bytes. | ||
The AES engine will automatically increment the counter up to the maximum BLKCNT, after which point it must be manually incremented and set again. | |||
== AES_MAC == | == AES_MAC == | ||