GPU/Internal Registers: Difference between revisions

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	This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG\|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.		This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG\|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

			[[Category:GPU]]