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GPU/Internal Registers (edit)

Revision as of 05:31, 2 December 2015

4,017 bytes added ,  05:31, 2 December 2015
→‎Texturing registers
Line 4,586: Line 4,586:  
| Enabled (0 = disabled, 1 = enabled)
 
| Enabled (0 = disabled, 1 = enabled)
 
|}
 
|}
 +
 +
=== GPUREG_TEXUNIT3_PROCTEX0 ===
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 +
{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-2
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| U-direction clamp
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|-
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| 3-5
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| V-direction clamp
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|-
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| 6-9
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| RGB mapping function
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|-
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| 10-13
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| Alpha mapping function
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|-
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| 14
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| Handle alpha separately (0 = don't separate, 1 = separate)
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|-
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| 15
 +
| Noise enabled (0 = disabled, 1 = enabled)
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|-
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| 16-17
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| U-direction shift
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|-
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| 18-19
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| V-direction shift
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|-
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| 20-27
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| float16 low 8 bits, Texture bias
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|}
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Clamp values:
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{| class="wikitable" border="1"
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! Value
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! Description
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|-
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| 0
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| Clamp to zero
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|-
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| 1
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| Clamp to edge
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|-
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| 2
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| Symmetrical repeat
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|-
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| 3
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| Mirrored repeat
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|-
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| 4
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| Pulse
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|}
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 +
Mapping function values:
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{| class="wikitable" border="1"
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! Value
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! Description
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|-
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| 0
 +
| U
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|-
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| 1
 +
| U2
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|-
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| 2
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| V
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|-
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| 3
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| V2
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|-
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| 4
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| U + V
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|-
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| 5
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| U2 + V2
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|-
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| 6
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| sqrt(U2 + V2)
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|-
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| 7
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| Minimum
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|-
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| 8
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| Maximum
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|-
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| 9
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| Rmax
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|}
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Shift values:
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{| class="wikitable" border="1"
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! Value
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! Description
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|-
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| 0
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| None
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|-
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| 1
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| Odd
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|-
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| 2
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| Even
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|}
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=== GPUREG_TEXUNIT3_PROCTEX1 ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-15
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| float16, U-direction noise phase
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|-
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| 16-31
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| fixed16, U-direction noise amplitude
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|}
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=== GPUREG_TEXUNIT3_PROCTEX2 ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-15
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| float16, V-direction noise phase
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|-
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| 16-31
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| fixed16, V-direction noise amplitude
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|}
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=== GPUREG_TEXUNIT3_PROCTEX3 ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-15
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| float16, U-direction noise frequency
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|-
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| 16-31
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| float16, V-direction noise frequency
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|}
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=== GPUREG_TEXUNIT3_PROCTEX4 ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-2
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| Minification filter
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|-
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| 3-10
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| 0x60
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|-
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| 11-18
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| Texture width
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|-
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| 19-26
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| float16 high 8 bits, Texture bias
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|}
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Minification filter values:
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{| class="wikitable" border="1"
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! Value
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! Description
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|-
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| 0
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| Nearest
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|-
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| 1
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| Linear
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|-
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| 2
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| Nearest, Mipmap Nearest
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|-
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| 3
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| Linear, Mipmap Nearest
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|-
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| 4
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| Nearest, Mipmap Linear
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|-
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| 5
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| Linear, Mipmap Linear
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|}
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=== GPUREG_TEXUNIT3_PROCTEX5 ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-7
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| Texture offset
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|-
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| 8-31
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| 0xE0C080
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|}
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=== GPUREG_PROCTEX_LUT ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-7
 +
| Index
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|-
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| 8-11
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| Reference table
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|}
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Reference tables:
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{| class="wikitable" border="1"
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! Value
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! Description
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|-
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| 0
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| Noise table
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|-
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| 2
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| RGB mapping function table
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|-
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| 3
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| Alpha mapping function table
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|-
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| 4
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| Color table
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|-
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| 5
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| Color difference table
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|}
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==== Noise Table ====
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128 elements:
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-11
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| unsigned fixed12, Value
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|-
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| 12-23
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| signed fixed12, Difference from next element
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|}
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==== RGB Mapping Function Table ====
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128 elements:
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-11
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| unsigned fixed12, Value
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|-
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| 12-23
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| signed fixed12, Difference from next element
 +
|}
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 +
==== Alpha Mapping Function Table ====
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128 elements:
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-11
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| unsigned fixed12, Value
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|-
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| 12-23
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| signed fixed12, Difference from next element
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|}
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==== Color Table ====
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256 elements:
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-7
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| u8, Red
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|-
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| 8-15
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| u8, Green
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|-
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| 16-23
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| u8, Blue
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|-
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| 24-31
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| u8, Alpha
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|}
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==== Color Difference Table ====
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256 elements:
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-7
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| signed fixed8, Red difference between current and next color table elements
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|-
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| 8-15
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| signed fixed8, Green difference between current and next color table elements
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|-
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| 16-23
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| signed fixed8, Blue difference between current and next color table elements
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|-
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| 24-31
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| signed fixed8, Alpha difference between current and next color table elements
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|}
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=== GPUREG_PROCTEX_LUT_DATA''i'' ===
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{| class="wikitable" border="1"
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! Bits
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! Description
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|-
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| 0-31
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| LUT data
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|}
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 +
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, sequentially.
    
== Framebuffer registers ==
 
== Framebuffer registers ==
Steveice10
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edits

Retrieved from "https://www.3dbrew.org/wiki/Special:MobileDiff/14774"