Corelink DMA Engines: Difference between revisions

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@@ Line 16: / Line 16: @@
       sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.
       uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4|8 = 12, 1|2|4|8 = 15
-      sint16_t max_burst_total; // @2 Burst length * burst size
+      sint16_t gather_granule_size; // @2
-      sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.
+      sint16_t gather_stride; // @4 Has to be >= 0, must not be 0 if peripheral_id == 0xFF.
-      sint16_t unk4; // @6
+      sint16_t scatter_granule_size; // @6
-      sint16_t transfer_stride?; // @8
+      sint16_t scatter_stride; // @8 Can be negative.
   }
@@ Line 28: / Line 28: @@
   .peripheral_id = 0xFF,
   .allowed_burst_sizes = 1 | 2 | 4 | 8,
-  .max_burst_total = 0x80,
+  .gather_granule_size = 0x80,
-  .transfer_size? = 0,
+  .gather_stride = 0,
-  .unk4 = 0x80,
+  .scatter_granule_size = 0x80,
-  .transfer_stride? = 0,
+  .scatter_stride = 0,
 If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.