PDN Registers: Difference between revisions
m typo fix |
Small cleanup |
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| Line 8: | Line 8: | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| [[# | | [[#PDN_SLEEP_CNT|PDN_SLEEP_CNT]] | ||
| 0x10141000 | | 0x10141000 | ||
| 2 | | 2 | ||
| Kernel11 | | Kernel11 | ||
|- | |- | ||
| style="background: green" | Yes | | style="background: green" | Yes | ||
| Line 129: | Line 129: | ||
|-style="border-top: double" | |-style="border-top: double" | ||
| style="background: red" | No | | style="background: red" | No | ||
| [[# | | [[#PDN_LGR_SOCMODE|PDN_LGR_SOCMODE]] | ||
| 0x10141300 | | 0x10141300 | ||
| 2 | | 2 | ||
| Line 135: | Line 135: | ||
|- | |- | ||
| style="background: red" | No | | style="background: red" | No | ||
| [[# | | [[#PDN_LGR_CNT|PDN_LGR_CNT]] | ||
| 0x10141304 | | 0x10141304 | ||
| 2 | | 2 | ||
| Line 141: | Line 141: | ||
|- | |- | ||
| style="background: red" | No | | style="background: red" | No | ||
| [[# | | [[#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3> | ||
| 0x10141310 | | 0x10141310 | ||
| 1*4 | | 1*4 | ||
| Line 147: | Line 147: | ||
|} | |} | ||
== | ==PDN_SLEEP_CNT== | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
| Line 159: | Line 159: | ||
|- | |- | ||
| 15 | | 15 | ||
| 1 = VRAM is | | 1 = VRAM is powered down | ||
|} | |} | ||
Kernel11 | Kernel11 powers down VRAM (it's unclear whether bit15 is power-down or self-refresh mode) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally writes to and polls this register. | ||
==PDN_WAKE_ENABLE== | ==PDN_WAKE_ENABLE== | ||
| Line 204: | Line 204: | ||
For each bit, write 1 to acknowledge, and 0 to clear (?). | For each bit, write 1 to acknowledge, and 0 to clear (?). | ||
==LGY_MODE== | ==LGY_MODE== | ||
| Line 360: | Line 349: | ||
PDN services holds reset for 0x30 Arm11 cycles. | PDN services holds reset for 0x30 Arm11 cycles. | ||
== | == PDN_LGR_SOCMODE == | ||
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read. | This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read. | ||
| Line 443: | Line 432: | ||
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05. | * 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05. | ||
== | == PDN_LGR_CNT == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
| Line 455: | Line 444: | ||
|} | |} | ||
Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] is set otherwise 1. | Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] (LGR2 supported) is set otherwise 1. | ||
== | == PDN_LGR_CPU_CNT<0-3> == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||