GPU/External Registers: Difference between revisions
m Fix a missing brace in calculation and make register more clear |
Get rid of misleading and wrong information, and add more researched PDC info (unfinished) |
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To make sense of these values, the 3DS must be held in a way, so that the bottom screen is in the left hand, and the top screen is in the right hand, and that way the first pixel will be in the top-left corner, as it should be. If the 3DS is held normally, the first pixel is in the bottom-left corner. | To make sense of these values, the 3DS must be held in a way, so that the bottom screen is in the left hand, and the top screen is in the right hand, and that way the first pixel will be in the top-left corner, as it should be. If the 3DS is held normally, the first pixel is in the bottom-left corner. | ||
All pixel and scanline timing values are 12bits, unless noted. This also applies to those fields where two u16 are combined into one register. Each u16 field is only 12bits in size. | All pixel and scanline timing values are 12bits, unless noted. This also applies to those fields where two u16 are combined into one register. Each u16 field is only 12bits in size. timin | ||
The horizontal timing parameter order is as follows: | |||
0x10 --> 0x14 --> 0x18 --> 0x60 low --> 0x04 --> 0x60 high --> 0x08 --> 0x0C. | |||
Timing starts from HCount == 0, then each absolute value in the beforementioned register chain triggers when HCount == register, latching the primitive display controller into a new mode. | |||
There is an inherent latch order, where if two simultenaous events occur, one event wins over another. | |||
Known latched modes (in no particular order): | |||
- HSync (triggers a line to the LCD to move to the next line) | |||
- Back porch (area between HSync and border being displayed) | |||
- Left border start (no image data is being displayed, just a configurable solid color) | |||
- Image start (pixel data is being DMA'd from video memory or main RAM) | |||
- Right border start/Image end (border color is being displayed after the main image) | |||
- Front porch (unknown where it happens) | |||
- Unknown synchronization/blanking (unknown where it happens) | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
Line 159: | Line 173: | ||
|- | |- | ||
| 0x04 | | 0x04 | ||
| | | HParam5 | ||
| | | | ||
|- | |- | ||
| 0x08 | | 0x08 | ||
| | | HParam7 | ||
| | | | ||
|- | |- | ||
| 0x0C | | 0x0C | ||
| | | HParam8 | ||
| | | | ||
|- | |- | ||
| 0x10 | | 0x10 | ||
| | | HParam1 | ||
| | | | ||
|- | |- | ||
| 0x14 | | 0x14 | ||
| | | HParam2 | ||
| | | | ||
|- | |- | ||
| 0x18 | | 0x18 | ||
| | | HParam3 | ||
| | | | ||
|- | |- | ||
| 0x1C | | 0x1C | ||
Line 205: | Line 208: | ||
|- | |- | ||
| 0x20 | | 0x20 | ||
| | | low u16: ??? | ||
high u16: ??? | |||
| | | ??? | ||
??? | |||
|- | |- | ||
| 0x24 | | 0x24 | ||
Line 275: | Line 273: | ||
| 0x5C | | 0x5C | ||
| ??? | | ??? | ||
| low u16: | | low u16: Image width (including some offset?) | ||
high u16: | high u16: Image height??? (seems to be unused) | ||
|- | |- | ||
| 0x60 | | 0x60 | ||
| ??? | | ??? | ||
| low u16: | | low u16: HParam4 | ||
high u16: | high u16: HParam6 | ||
|- | |- | ||
| 0x64 | | 0x64 | ||
Line 297: | Line 295: | ||
|- | |- | ||
| 0x70 | | 0x70 | ||
| Framebuffer format | | Framebuffer format and other settings | ||
| | | Bit 0-2: framebuffer format | ||
Bit 3: null (unwritable) | |||
Bit 4-7: unknown | |||
Bit 8-9: DMA size | |||
Bit 10-15: null (unwritable) | |||
Bit 16-31: unknown | |||
DMA sizes (in bytes): | |||
0 - 64 | |||
1 - 128 | |||
2 - 256 | |||
3 - ??? | |||
|- | |- | ||
| 0x74 | | 0x74 |