GSP Shared Memory: Difference between revisions

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TransferEngine
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This command sets the GPU [[GPU/External_Registers#Memory_Fill|Memory Fill registers]].
This command sets the [[GPU/External_Registers#Memory_Fill|Memory Fill registers]].


Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be < its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.
Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be less than its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.


=== Trigger Display Transfer ===
=== Trigger Display Transfer ===
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|-
|-
| 1
| 1
| Input framebuffer address
| Source address
|-
|-
| 2
| 2
| Output framebuffer address
| Destination address
|-
|-
| 3
| 3
| Input framebuffer [[GPU|dimensions]]
| Source dimensions
|-
|-
| 4
| 4
| Output framebuffer dimensions
| Output dimensions
|-
|-
| 5
| 5
| [[GPU|Flags]], for applications this is 0x1001000 for the main screen, and 0x1000 for the sub screen.
| Flags
|-
|-
| 7-6
| 7-6
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This command converts the specified addresses to physical addresses, then writes these physical addresses and parameters to the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM.
This command sets the [[GPU/External_Registers#Transfer_Engine|Display Transfer registers]].


The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers.
No error checking is performed on the parameters. Addresses should be aligned to 8 bytes and should be in linear, QTM or VRAM memory, otherwise PA 0 is used.
 
Display transfers are performed asynchronously, so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data.
 
The minimum supported dimension for output is 64x64, anything lower will hang the engine.


=== Trigger Texture Copy ===
=== Trigger Texture Copy ===
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|-
|-
| 1
| 1
| Input buffer address.
| Source address
|-
|-
| 2
| 2
| Output buffer address.
| Destination address
|-
|-
| 3
| 3
| Total bytes to copy, not including gaps.
| Size
|-
|-
| 4
| 4
| Bits 0-15: Size of input line, in bytes. Bits 16-31: Gap between input lines, in bytes.
| Line width <nowiki>|</nowiki> (gap << 16)
|-
|-
| 5
| 5
| Same as 4, but for the output.
| Same as above, for the destination
|-
|-
| 6
| 6
| Flags, corresponding to the [[GPU/External_Registers#Transfer_Engine|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is always set, bit 2 is set if any output dimension is smaller than the input, and other bits are always 0.
| Flags
|-
|-
| 7
| 7
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This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.
This command sets the [[GPU/External_Registers#TextureCopy|Texture Copy registers]]. Note that GSP doesn't enforce bit3 of the flags to be set.
 
No error checking is performed on the parameters. Addresses and size should be aligned to 8 bytes, and the addresses should be in linear, QTM or VRAM memory, otherwise PA 0 is used.


=== Flush Cache Regions ===
=== Flush Cache Regions ===

Revision as of 16:24, 12 May 2025

This page describes the structure of the GSP shared memory. Interrupt, framebuffer, and GX command data is stored here.

Interrupt Queue

The Interrupt queue is located at sharedMemBase + (clientID * 0x40).

Index Byte Description
0x0 Offset from the count where to save incoming interrupts
0x1 Count (max 0x20 for PDC, 0x34 for others)
0x2 Missed other interrupts (set to 1 when 0 and count >= 0x34)
0x3 Flags (bit0 = skip PDC)
0x4-0x7 Missed PDC0 (incremented when flags.bit0 is clear and count >= 0x20)
0x8-0xB Missed PDC1 (same as above)
0xC-0x3F Interrupt list (u8) (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop, 3=PDC1/VBlankBottom, 4=PPF, 5=P3D, 6=DMA)

GSP fills the interrupt list, then triggers the event set with RegisterInterruptRelayQueue for the specified process(es).

PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.

Framebuffer Info

The framebuffer info structure for the top LCD is located at sharedMemBase + 0x200 + (clientID * 0x80).

The framebuffer info structure for the bottom LCD is located at sharedMemBase + 0x240 + (clientID * 0x80).

Framebuffer Info Header

Index Byte Description
0 Framebuffer info entry index
1 Flags (bit0 = client has set new data)
3-2 Padding

Framebuffer Info Structure

Index Word Description
0 Active framebuffer (0 = first, 1 = second)
1 Left framebuffer VA
2 Right framebuffer VA (top screen only)
3 Stride (offset 0x90)
4 Format
5 Status (offset 0x78)
6 ? ("Attribute")

When a process sets this framebuffer info, it sets index to (index+1) & 1. Then it writes the framebuffer info entry, and sets flag to value 1. The GSP module loads this framebuffer info entry data into GSP state once the GPU finishes processing GX commands 3 or 4. Once the GSP module finishes loading this framebuffer info, it sets flag to value 0, then it will not load the framebuffer info again until flag is value 1. After loading this entry data into GSP state, the GSP module then writes this framebuffer state to the LCD registers. GSP module automatically updates the LCD framebuffer registers each time GX commands 3 or 4 finish, even when this shared memory data was not updated by the application.(GSP module toggles the active framebuffer register when automatically updating LCD registers, when shared memory data is not used)

The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.

3D Slider and 3D LED

See Configuration Memory.

Command Queue

The command queue is located at sharedMemBase + 0x800 + (clientID * 0x200). It consists of an header followed by at most 15 command entries. Each command entry is of size 0x20 and has an header followed by command specific parameters.

After adding a command, TriggerCmdReqQueue must be used to start command processing (official code does so when the total commands field is 1).

Command Queue Header

Index Byte Description
0 Index of the command to process, this is incremented by GSP before handling the command
1 Total commands to process, this is incremented by the application when adding the command to the queue, and decremented by GSP before handling the command
2 Status (bit0 = halted, bit7 = fatal error)
3 When bit0 is set, further processing of commands is halted until the client resets the flag and calls TriggerCmdReqQueue
7-4 Result code for the last command which failed

GSP checks for status.bit0 and optionally avoids handling further commands, however the check is done by equality, which means it will always fail if status.bit7 is also set (and thus other commands will be processed). This bug prevents the halting logic from working propertly, but can be worked around by keeping bit0 of word3 set, as that will force halting on each iteration.

Command Header

Index Byte Description
0 Command ID
1 Unused
2 When bit0 is set, GSP stops processing further commands (can be used for packing together sets of commands)
3 When set, the command fails if GSP is busy handling any other command; otherwise, it only fails if GSP is busy handling a command of the same kind

Commands

Addresses specified in parameters are virtual addresses. Address and size parameters except for command 0 and command 5 must be 8-byte aligned.

Trigger DMA Request

Index Word Description
0 Command header (ID = 0x00)
1 Source address
2 Destination address
3 Size
6-4 Unused
7 Flush source (0 = don't flush, 1 = flush)

This command issues a DMA request as the calling process. When the destination address is within VRAM, GSP places itself as the destination process, this makes it possible to transfer data in VRAM without needing it listed in the destination process exheader mappings. Otherwise, both source and destination of the DMA request are the calling process.

The source buffer must be mapped as readable in the source process, while the destination address must be mapped as writable in the destination process. When flushing is enabled and the source address is above VRAM, svcFlushProcessDataCache is used to flush the source buffer.

Trigger Command List Processing

Index Word Description
0 Command header (ID = 0x01)
1 Buffer address
2 Buffer size
3 Update gas additive blend results (0 = don't update, 1 = update)
6-4 Unused
7 Flush buffer (0 = don't flush, 1 = flush)

This command sets the Command List registers, and optionally updates gas additive blend results after command processing has ended.

No error checking is performed on the parameters. Address and size should be both aligned to 8 bytes, and the address should be in linear, QTM or VRAM memory, otherwise PA 0 is used. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.

Trigger Memory Fill

Index Word Description
0 Command header (ID = 0x02)
1 Buffer 0 start address
2 Buffer 0 value
3 Buffer 0 end address
4 Buffer 1 start address
5 Buffer 1 value
6 Buffer 1 end address
7 Control0 | (Control1 << 16)

This command sets the Memory Fill registers.

Addresses should be aligned to 8 bytes and must be in linear, QTM or VRAM memory, otherwise error 0xE0E02BF5 (GSP_INVALID_ADDRESS) is returned. The start address for a buffer must be less than its end address, else the same error is returned. If the start address for a buffer is 0, that buffer is skipped; otherwise, its relative PSC unit is used for the fill operation.

Trigger Display Transfer

Index Word Description
0 Command header (ID = 0x03)
1 Source address
2 Destination address
3 Source dimensions
4 Output dimensions
5 Flags
7-6 Unused

This command sets the Display Transfer registers.

No error checking is performed on the parameters. Addresses should be aligned to 8 bytes and should be in linear, QTM or VRAM memory, otherwise PA 0 is used.

Trigger Texture Copy

Index Word Description
0 Command header (ID = 0x04)
1 Source address
2 Destination address
3 Size
4 Line width | (gap << 16)
5 Same as above, for the destination
6 Flags
7 Unused

This command sets the Texture Copy registers. Note that GSP doesn't enforce bit3 of the flags to be set.

No error checking is performed on the parameters. Addresses and size should be aligned to 8 bytes, and the addresses should be in linear, QTM or VRAM memory, otherwise PA 0 is used.

Flush Cache Regions

Index Word Description
0 Command header (ID = 0x05)
1 Buf0 address
2 Buf0 size
3 Buf1 address
4 Buf1 size
5 Buf2 address
6 Buf2 size
7 Unused

The application buffer addresses specified in the parameters are used with svcFlushProcessDataCache. The input buf0 size must not be zero. When buf1 size is zero, svcFlushProcessDataCache() for buf1 and buf2 are skipped. When buf2 size is zero, svcFlushProcessDataCache() for buf2 is skipped.

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