Configuration Memory: Difference between revisions

Line 97: Line 97:
|-
|-
| 1
| 1
| ?
|-
| 2
| Set for debug units
| Set for debug units
|-
|-
| 3-7
| 2-7
| ?
| ?
|}
|}


Normally this register is all-zero, however bit2 in this register is set by the ARM11 kernel when ARM debug CP14 DSCR bit14 is set. [[NS]] loads the menu TID from MENUTID when bits 1-7 of this register are clear. [[ErrDisp]] will display development error info when bit0 is clear.
Normally this register is all-zero, however bit1 in this field is set by the ARM11 kernel when ARM debug CP14 DSCR bit14 is set. [[NS]] loads the menu TID from MENUTID when bits 1-7 of this register are clear. [[ErrDisp]] will display development error info when bit0 is clear.


=== APPMEMALLOC ===
=== APPMEMALLOC ===