GPU/Shader Instruction Set: Difference between revisions
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== Registers == | == Registers == | ||
It is not yet fully understood how registers are organized. It does however seem that registers are separated into various banks, some RO, some WO and some RW. Because of this separation, a given register ID may not refer to the same register value when it is used as SRC or as DST. | It is not yet fully understood how registers are organized. It does however seem that registers are separated into various banks, some RO, some WO and some RW. Because of this separation, a given register ID may not refer to the same register value when it is used as SRC or as DST. | ||
Attribute (input, RO) registers are located within the 0x0-0x10 range. What data they are fed is specified by the CPU. | Attribute (input, RO) registers are located within the 0x0-0x10 range. What data they are fed is specified by the CPU. | ||
Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU. | Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU. | ||
Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data. | Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data. | ||