GPU/Shader Instruction Set: Difference between revisions
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Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU. | Output (WO) registers are also located within the 0x0-0x10 range. What data they are contain is specified by the CPU. | ||
Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data. | Registers within the 0x20-0x40 ranges seem to be RW. They contain uniforms, such as matrix data. | ||
It appears that writing twice to the same output register can cause problems, such as the GPU hanging. | |||