CSND Registers: Difference between revisions
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=0x1EC03000= | |||
{| class="wikitable" border="1" | |||
! NAME | |||
! PHYSICAL ADDRESS | |||
! WIDTH | |||
! DESCRIPTION | |||
|- | |||
| REG_DSP_FIFO | |||
| 0x1ED03000 | |||
| 2 | |||
| | |||
|- | |||
| REG_DSP_?? | |||
| 0x1ED03004 | |||
| 2 | |||
| ??? | |||
|- | |||
| REG_DSP_FIFO_CNT | |||
| 0x1ED03008 | |||
| 2 | |||
| | |||
|- | |||
| REG_DSP_?? | |||
| 0x1ED03010 | |||
| 2 | |||
| ??? | |||
|- | |||
| REG_DSP_STATUS | |||
| 0x1ED0300C | |||
| 2 | |||
| | |||
|- | |||
| REG_DSP_?? | |||
| 0x1ED03014 | |||
| 2 | |||
| ??? | |||
|- | |||
| REG_DSP_?? | |||
| 0x1ED03018 | |||
| 2 | |||
| ??? | |||
|- | |||
| REG_DSP_?? | |||
| 0x1ED0301C | |||
| 2 | |||
| ??? | |||
|- | |||
| REG_DSP_PORT<0-2> | |||
| 0x1ED03020 | |||
| 3*8=0x18 | |||
| | |||
|} | |||
=== REG_DSP_STATUS === | |||
bit1,8: FIFO WRITE ERRORS? | |||
bit6: FIFO_READ_READY | |||
bit7: FIFO_WRITE_READY | |||
bit9: ??? | |||
bit10-12: PORT<0-2>_RECV_READY | |||
bit13-15: PORT<0-2>_SEND_READY | |||
=0x1EC03400= | =0x1EC03400= | ||
The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots. | The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots. | ||