Line 70: |
Line 70: |
| | [[#CFG11_SPI_CNT|CFG11_SPI_CNT]] | | | [[#CFG11_SPI_CNT|CFG11_SPI_CNT]] |
| | 0x101401C0 | | | 0x101401C0 |
− | | 4 | + | | 2 |
| | [[SPI Services]], TwlBg | | | [[SPI Services]], TwlBg |
| |- | | |- |
Line 116: |
Line 116: |
| |-style="border-top: double" | | |-style="border-top: double" |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | CFG11_GPU_STATUS? | + | | CFG11_GPU_STATUS |
| | 0x10141000 | | | 0x10141000 |
− | | 4 | + | | 2 |
| | Kernel11, TwlBg | | | Kernel11, TwlBg |
| |- | | |- |
Line 164: |
Line 164: |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | ? | + | | [[#CFG11_TWLAGB_HIDEMU_MASK|CFG11_TWLAGB_HIDEMU_MASK]] |
| | 0x10141110 | | | 0x10141110 |
| | 2 | | | 2 |
Line 170: |
Line 170: |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | ? | + | | [[#CFG11_TWLAGB_HIDEMU_PAD|CFG11_TWLAGB_HIDEMU_PAD]] |
| | 0x10141112 | | | 0x10141112 |
| | 2 | | | 2 |
Line 179: |
Line 179: |
| | 0x10141114 | | | 0x10141114 |
| | 2 | | | 2 |
− | | [[CDC Services]], TwlBg | + | | [[Codec Services]], TwlBg |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
Line 185: |
Line 185: |
| | 0x10141116 | | | 0x10141116 |
| | 2 | | | 2 |
− | | [[CDC Services]], TwlBg | + | | [[Codec Services]], TwlBg |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
Line 210: |
Line 210: |
| | 0x10141200 | | | 0x10141200 |
| | 4 | | | 4 |
− | | Boot11, Kernel11, [[PDN Services]] | + | | Boot11, Kernel11, [[PDN Services]], TwlBg |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
Line 216: |
Line 216: |
| | 0x10141204 | | | 0x10141204 |
| | 4 | | | 4 |
− | | Boot11, Kernel11 | + | | Boot11, Kernel11, TwlBg |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | CFG11_GPU_CNT3 | + | | CFG11_GPU_FCRAM_CNT |
| | 0x10141210 | | | 0x10141210 |
| | 2 | | | 2 |
Line 237: |
Line 237: |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | CFG11_DSP_CNT | + | | [[#CFG11_DSP_CNT|CFG11_DSP_CNT]] |
| | 0x10141230 | | | 0x10141230 |
| | 1 | | | 1 |
Line 358: |
Line 358: |
| |- | | |- |
| | 0 | | | 0 |
− | | Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze. | + | | Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze. This enables the New 3DS FCRAM extension. |
| |- | | |- |
| | 1-2 | | | 1-2 |
Line 367: |
Line 367: |
| |} | | |} |
| | | |
− | [[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG: | + | [[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_SOCINFO: |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Register value | | ! Register value |
| ! Higher-clockrate bit set in svcKernelSetState Param0 | | ! Higher-clockrate bit set in svcKernelSetState Param0 |
− | ! CFG11_MPCORE_CFG bit2 set | + | ! CFG11_SOCINFO bit2 set |
| ! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state | | ! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state |
| ! Clock-rate multiplier | | ! Clock-rate multiplier |
Line 405: |
Line 405: |
| |} | | |} |
| | | |
− | Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). | + | Note that the above CFG11_SOCINFO bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). |
| | | |
| The following register value(s) were tested on New3DS by patching the kernel: | | The following register value(s) were tested on New3DS by patching the kernel: |
Line 430: |
Line 430: |
| |- | | |- |
| | 0 | | | 0 |
− | | Power on 3rd ARM11 MPCore maybe? | + | | ? |
| |- | | |- |
| | 8 | | | 8 |
− | | Power on 4th ARM11 MPCore maybe? | + | | ? |
| |} | | |} |
| + | |
| + | Kernel11 sets this to 0x101 when bit 2 in [[#CFG11_SOCINFO|CFG11_SOCINFO]] is set otherwise 1. |
| | | |
| == CFG11_MPCORE_BOOTCNT<0-3> == | | == CFG11_MPCORE_BOOTCNT<0-3> == |
Line 543: |
Line 545: |
| | Wifi-related? Set to 1 very early in NWM-module. | | | Wifi-related? Set to 1 very early in NWM-module. |
| |} | | |} |
| + | |
| + | ==CFG11_TWLAGB_HIDEMU_MASK== |
| + | Set bits will use the corresponding values from [[#CFG11_TWLAGB_HIDEMU_PAD|CFG11_TWLAGB_HIDEMU_PAD]] instead of allowing the hardware to read it from [[HID_Registers#HID_PAD|HID_PAD]]. |
| + | |
| + | This is set to 0x1FFF (all buttons and the debug key) and [[#CFG11_TWLAGB_HIDEMU_PAD|CFG11_TWLAGB_HIDEMU_PAD]] is set to 0 when the "Close this software and return to HOME Menu?" dialog is shown to prevent the button presses from propagating to the DS/GBA CPU. |
| + | |
| + | ==CFG11_TWLAGB_HIDEMU_PAD== |
| + | Works the same way as [[HID_Registers#HID_PAD|HID_PAD]], but the values set here are only replaced in the HID_PAD seen by the DS/GBA CPU when the corresponding bits in [[#CFG11_TWLAGB_HIDEMU_MASK|CFG11_TWLAGB_HIDEMU_MASK]] are set. |
| | | |
| ==CFG11_GPU_CNT== | | ==CFG11_GPU_CNT== |
| This one seems to control the LCD/GPU/Backlight. | | This one seems to control the LCD/GPU/Backlight. |
| | | |
− | Bit0: Enable GPU registers at 0x10400000+. | + | Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled). |
− | Bit16: Turn on LCD backlight. | + | When this is unset VRAM is not accessible and triggers exceptions. |
| + | |
| + | Bits 1..6: other nRESET bits. |
| + | |
| + | Bit16: Enable/Turn on LCD backlight. |
| + | |
| + | PDN uses a 12 Arm11 cycle delay to deassert reset. |
| | | |
| ==CFG11_GPU_CNT2== | | ==CFG11_GPU_CNT2== |
| Bit0: Power on GPU? | | Bit0: Power on GPU? |
| | | |
− | ==CFG11_GPU_CNT3== | + | ==CFG11_GPU_FCRAM_CNT== |
− | Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash. | + | Bit1: Enable/disable FCRAM. |
| + | Bit2: Enable/disable operation in progress. |
| | | |
| ==CFG11_CODEC== | | ==CFG11_CODEC== |
Line 568: |
Line 585: |
| | | |
| bit0 = unknown, bit1 = turn on/off cameras, rest = always 0. | | bit0 = unknown, bit1 = turn on/off cameras, rest = always 0. |
| + | |
| + | ==CFG11_DSP_CNT== |
| + | This is the power register used for the [[CFG11_Services|PDN Services]] DSP service. |
| + | |
| + | bit0: NRESET (active low). Unset to reset/hold reset. |
| + | bit1: enable bit. |
| + | |
| + | PDN services holds reset for 0x30 Arm11 cycles. |