Changes

|-

|-

| style="background: green" | Yes

| style="background: green" | Yes

| [[#AES_MACBLKCNT|AES_MACBLKCNT]]

| [[#AES_MACEXTRABLKCNT|AES_MACBLKCNT]]

| 0x10009004

| 0x10009004

| 2

| 2

Changing the input word order triggers the key/keyX/keyY FIFOs to be flushed.

Changing the input word order triggers the key/keyX/keyY FIFOs to be flushed.

== AES_MACBLKCNT ==

== AES_MACEXTRABLKCNT ==

(CCM-MAC length)>>4, i.e. the size of the CCM-MAC to work with, in blocks

(CCM-MAC extra data length)>>4, i.e. the number of block of CCM-MAC extra data.

== AES_BLKCNT ==

== AES_BLKCNT ==

== Endianness and word order ==

== Endianness and word order ==

When writing to the AES_CTR, AES_MAC or AES_KEY0/1/2/3 register, the hardware will process the written data according to the current input endianness specified in AES_CNT. However, the current specified input word order will not be honored for this register, and always defaults to reversed word order. Therefore, for normal word order, the reversal must be carried out manually if required.

When writing to the AES_CTR, AES_MAC or AES_KEY0/1/2/3 register, the hardware will process the written data according to the current input endianness specified in AES_CNT. This means that the byte ordering within each word is endian swapped accordingly but the word ordering of the register remains little endian.

== CCM mode pitfall ==

== CCM mode pitfall ==