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Line 492: − + + + − For the new FCRAM DMA cutoff, it protects 0x30000000-(size) where size is 0x800000*x. This can be used to protect all of the upper FCRAM except for the first 0x800000-bytes (lowest protection addr via x=0xF is 0x28800000).+ − + Line 502:
Line 506: − + − Bit0: Enable wifi.+ + + + + + + + + Line 523:
Line 535: − + − Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.+ + + + + + + + + − + − + + + + + + + − + − + + Line 550:
Line 577: + + + + + + + +
→CFG11_GPU_CNT
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]
| [[#CFG11_WIFICNT|CFG11_WIFICNT]]
| 0x10140180
| 0x10140180
| 1
| 1
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]
| 0x101401C0
| 0x101401C0
| 4
| 2
| [[SPI Services]], TwlBg
| [[SPI Services]], TwlBg
|-
|-
|-style="border-top: double"
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| CFG11_GPU_STATUS?
| CFG11_GPU_STATUS
| 0x10141000
| 0x10141000
| 4
| 2
| Kernel11, TwlBg
| Kernel11, TwlBg
|-
|-
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| CFG11_WIFI?
| [[#CFG11_WIFIUNK|CFG11_WIFIUNK]]
| 0x1014110C
| 0x1014110C
| 1
| 1
| 0x10141114
| 0x10141114
| 2
| 2
| [[CODEC Services]], TwlBg
| [[Codec Services]], TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10141116
| 0x10141116
| 2
| 2
| [[CODEC Services]], TwlBg
| [[Codec Services]], TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10141200
| 0x10141200
| 4
| 4
| Boot11, Kernel11, [[PDN Services]]
| Boot11, Kernel11, [[PDN Services]], TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10141204
| 0x10141204
| 4
| 4
| Boot11, Kernel11
| Boot11, Kernel11, TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| CFG11_GPU_CNT3
| CFG11_GPU_FCRAM_CNT
| 0x10141210
| 0x10141210
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| CFG11_DSP_CNT
| [[#CFG11_DSP_CNT|CFG11_DSP_CNT]]
| 0x10141230
| 0x10141230
| 1
| 1
|-
|-
| 0
| 0
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze. This enables the New 3DS FCRAM extension.
|-
|-
| 1-2
| 1-2
|}
|}
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_SOCINFO:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Register value
! Register value
! Higher-clockrate bit set in svcKernelSetState Param0
! Higher-clockrate bit set in svcKernelSetState Param0
! CFG11_MPCORE_CFG bit2 set
! CFG11_SOCINFO bit2 set
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state
! Clock-rate multiplier
! Clock-rate multiplier
|}
|}
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).
Note that the above CFG11_SOCINFO bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).
The following register value(s) were tested on New3DS by patching the kernel:
The following register value(s) were tested on New3DS by patching the kernel:
|-
|-
| 0
| 0
| Power on 3rd ARM11 MPCore maybe?
| ?
|-
|-
| 8
| 8
| Power on 4th ARM11 MPCore maybe?
| ?
|}
|}
Kernel11 sets this to 0x101 when bit 2 in [[#CFG11_SOCINFO|CFG11_SOCINFO]] is set otherwise 1.
== CFG11_MPCORE_BOOTCNT<0-3> ==
== CFG11_MPCORE_BOOTCNT<0-3> ==
| style="background: green" | Yes
| style="background: green" | Yes
| 3-0
| 3-0
| Old FCRAM DMA cutoff size
| Old FCRAM DMA cutoff size, 0 = no protection.
|-
|-
| style="background: red" | No
| style="background: red" | No
|}
|}
For the old FCRAM DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.
For the QTM DMA cutoff, it appears to start at 0x1F400000-(0x100000*x) length 0x100000*x
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.
On cold boot this reg is set to 0.
On cold boot this reg is set to 0.
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].
==CFG11_WIFI_CNT==
==CFG11_WIFICNT==
{| class="wikitable" border="1"
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 0
| Enable wifi subsystem
|}
==CFG11_TWLMODE_0==
==CFG11_TWLMODE_0==
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.
==CFG11_WIFI?==
==CFG11_WIFIUNK==
{| class="wikitable" border="1"
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 4
| Wifi-related? Set to 1 very early in NWM-module.
|}
==CFG11_GPU_CNT==
==CFG11_GPU_CNT==
This one seems to control the LCD/GPU/Backlight.
This one seems to control the LCD/GPU/Backlight.
Bit0: Enable GPU registers at 0x10400000+.
Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled).
Bit16: Turn on LCD backlight.
When this is unset VRAM is not accessible and triggers exceptions.
Bits 1..6: other nRESET bits.
Bit16: Enable/Turn on LCD backlight.
PDN uses a 12 Arm11 cycle delay to deassert reset.
==CFG11_GPU_CNT2==
==CFG11_GPU_CNT2==
Bit0: Power on GPU?
Bit0: Power on GPU?
==CFG11_GPU_CNT3==
==CFG11_GPU_FCRAM_CNT==
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.
Bit1: Enable/disable FCRAM.
Bit2: Enable/disable operation in progress.
==CFG11_CODEC==
==CFG11_CODEC==
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
==CFG11_DSP_CNT==
This is the power register used for the [[CFG11_Services|PDN Services]] DSP service.
bit0: NRESET (active low). Unset to reset/hold reset.
bit1: enable bit.
PDN services holds reset for 0x30 Arm11 cycles.