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Line 458: − + − + − ldr pc, [pc]+ − + − Bit0: Enable wifi.+ + + + + + + + + + + + + + + + + + + + + + + + + − + + + + + + + + + + + + + + + + + + + + + + + + + + Line 475:
Line 526: − + − + − + − + − Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.+ + + + + + + + + + + + + + + + + − + − + − + + + + + − + + + − + − + + − + − + − + − + − + + + + + + + + +
add some legacy HID emulation info
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SHAREDWRAM_32K_DATA|PDN_SHAREDWRAM_32K_DATA]]<0-7>
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7>
| 0x10140000
| 0x10140000
| 1*8
| 1*8
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SHAREDWRAM_32K_CODE|PDN_SHAREDWRAM_32K_CODE]]<0-7>
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7>
| 0x10140008
| 0x10140008
| 1*8
| 1*8
| 0x10140100
| 0x10140100
| 2
| 2
|
|
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10140102
| 0x10140102
| 2
| 2
|
|
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_FIQ_CNT|PDN_FIQ_CNT]]
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]
| 0x10140104
| 0x10140104
| 1
| 1
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]
| 0x10140140
| 0x10140140
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_WIFI_CNT|PDN_WIFI_CNT]]
| [[#CFG11_WIFICNT|CFG11_WIFICNT]]
| 0x10140180
| 0x10140180
| 1
| 1
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SPI_CNT|PDN_SPI_CNT]]
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]
| 0x101401C0
| 0x101401C0
| 4
| 2
| [[SPI Services]], TwlBg
| [[SPI Services]], TwlBg
|-
|-
| 0x10140200
| 0x10140200
| 4
| 4
|
|
|-style="border-top: double"
|-style="border-top: double"
| style="background: red" | No
| style="background: red" | No
|-
|-
| style="background: red" | No
| style="background: red" | No
| [[#PDN_BOOTROM_OVERLAY_CNT|PDN_BOOTROM_OVERLAY_CNT]]
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]
| 0x10140420
| 0x10140420
| 1
| 1
|-
|-
| style="background: red" | No
| style="background: red" | No
| [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]]
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]
| 0x10140424
| 0x10140424
| 4
| 4
| 0x10140428
| 0x10140428
| 4
| 4
|
|
|-style="border-top: double"
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SOCINFO|PDN_SOCINFO]]
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]
| 0x10140FFC
| 0x10140FFC
| 2
| 2
|-style="border-top: double"
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| PDN_GPU_STATUS?
| CFG11_GPU_STATUS
| 0x10141000
| 0x10141000
| 4
| 2
| Kernel11, TwlBg
| Kernel11, TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| PDN_PTM_0
| CFG11_PTM_0
| 0x10141008
| 0x10141008
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| PDN_PTM_1
| CFG11_PTM_1
| 0x1014100C
| 0x1014100C
| 4
| 4
|-style="border-top: double"
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_TWLMODE_0|PDN_TWLMODE_0]]
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]
| 0x10141100
| 0x10141100
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_TWLMODE_1|PDN_TWLMODE_1]]
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]
| 0x10141104
| 0x10141104
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_TWLMODE_2|PDN_TWLMODE_2]]
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]
| 0x10141108
| 0x10141108
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_TWLMODE_HID|PDN_TWLMODE_HID]]
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]
| 0x1014110A
| 0x1014110A
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| PDN_WIFI?
| [[#CFG11_WIFIUNK|CFG11_WIFIUNK]]
| 0x1014110C
| 0x1014110C
| 1
| 1
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_TWLAGB_HIDEMU_MASK|CFG11_TWLAGB_HIDEMU_MASK]]
| 0x10141110
| 0x10141110
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_TWLAGB_HIDEMU_PAD|CFG11_TWLAGB_HIDEMU_PAD]]
| 0x10141112
| 0x10141112
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_CODEC|PDN_CODEC_0]]
| [[#CFG11_CODEC|CFG11_CODEC_0]]
| 0x10141114
| 0x10141114
| 2
| 2
| [[CODEC Services]], TwlBg
| [[Codec Services]], TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_CODEC|PDN_CODEC_1]]
| [[#CFG11_CODEC|CFG11_CODEC_1]]
| 0x10141116
| 0x10141116
| 2
| 2
| [[CODEC Services]], TwlBg
| [[Codec Services]], TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
|-style="border-top: double"
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_GPU_CNT|PDN_GPU_CNT]]
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]
| 0x10141200
| 0x10141200
| 4
| 4
| Boot11, Kernel11, [[PDN Services]]
| Boot11, Kernel11, [[PDN Services]], TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_GPU_CNT2|PDN_GPU_CNT2]]
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]
| 0x10141204
| 0x10141204
| 4
| 4
| Boot11, Kernel11
| Boot11, Kernel11, TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| PDN_GPU_CNT3
| CFG11_GPU_FCRAM_CNT
| 0x10141210
| 0x10141210
| 2
| 2
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_CODEC_CNT|PDN_CODEC_CNT]]
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]
| 0x10141220
| 0x10141220
| 1
| 1
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_CAMERA_CNT|PDN_CAMERA_CNT]]
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]
| 0x10141224
| 0x10141224
| 1
| 1
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| PDN_DSP_CNT
| [[#CFG11_DSP_CNT|CFG11_DSP_CNT]]
| 0x10141230
| 0x10141230
| 1
| 1
|-style="border-top: double"
|-style="border-top: double"
| style="background: red" | No
| style="background: red" | No
| [[#PDN_MPCORE_CLKCNT|PDN_MPCORE_CLKCNT]]
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]
| 0x10141300
| 0x10141300
| 2
| 2
|-
|-
| style="background: red" | No
| style="background: red" | No
| [[#PDN_MPCORE_CNT|PDN_MPCORE_CNT]]
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]
| 0x10141304
| 0x10141304
| 2
| 2
|-
|-
| style="background: red" | No
| style="background: red" | No
| [[#PDN_MPCORE_BOOTCNT<0-3>|PDN_MPCORE_BOOTCNT]]<0-3>
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3>
| 0x10141310
| 0x10141310
| 1*4
| 1*4
|}
|}
== PDN_SHAREDWRAM_32K_DATA ==
== CFG11_SHAREDWRAM_32K_DATA ==
Used for mapping 32K chunks of shared WRAM for DSP data.
Used for mapping 32K chunks of shared WRAM for DSP data.
|}
|}
== PDN_SHAREDWRAM_32K_CODE ==
== CFG11_SHAREDWRAM_32K_CODE ==
Used for mapping 32K chunks of shared WRAM for DSP data.
Used for mapping 32K chunks of shared WRAM for DSP data.
|}
|}
== PDN_FIQ_CNT ==
== CFG11_FIQ_CNT ==
Writing bit1 to this register disables FIQ interrupts.
Writing bit1 to this register disables FIQ interrupts.
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.
It is cleared when binding that software interrupt to an event and just before that event is signaled.
It is cleared when binding that software interrupt to an event and just before that event is signaled.
== PDN_SPI_CNT ==
== CFG11_SPI_CNT ==
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
== PDN_BOOTROM_OVERLAY_CNT ==
== CFG11_BOOTROM_OVERLAY_CNT ==
Bit0: Enable bootrom overlay functionality.
Bit0: Enable bootrom overlay functionality.
== PDN_BOOTROM_OVERLAY_VAL ==
== CFG11_BOOTROM_OVERLAY_VAL ==
The 32-bit value to overlay data-reads to bootrom with. See [[#PDN_MPCORE_BOOTCNT|PDN_MPCORE_BOOTCNT]].
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].
== PDN_SOCINFO ==
== CFG11_SOCINFO ==
Read-only register.
Read-only register.
|}
|}
== PDN_MPCORE_CLKCNT ==
== CFG11_MPCORE_CLKCNT ==
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
|-
|-
| 0
| 0
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze. This enables the New 3DS FCRAM extension.
|-
|-
| 1-2
| 1-2
|}
|}
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of PDN_MPCORE_CFG:
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_SOCINFO:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Register value
! Register value
! Higher-clockrate bit set in svcKernelSetState Param0
! Higher-clockrate bit set in svcKernelSetState Param0
! PDN_MPCORE_CFG bit2 set
! CFG11_SOCINFO bit2 set
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state
! Clock-rate multiplier
! Clock-rate multiplier
|}
|}
Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).
Note that the above CFG11_SOCINFO bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).
The following register value(s) were tested on New3DS by patching the kernel:
The following register value(s) were tested on New3DS by patching the kernel:
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
== PDN_MPCORE_CNT ==
== CFG11_MPCORE_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
|-
|-
| 0
| 0
| Power on 3rd ARM11 MPCore maybe?
| ?
|-
|-
| 8
| 8
| Power on 4th ARM11 MPCore maybe?
| ?
|}
|}
== PDN_MPCORE_BOOTCNT<0-3> ==
Kernel11 sets this to 0x101 when bit 2 in [[#CFG11_SOCINFO|CFG11_SOCINFO]] is set otherwise 1.
== CFG11_MPCORE_BOOTCNT<0-3> ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]].
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:
ldr pc, [pc]
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.
==PDN_WIFI_CNT==
==CFG11_GPUPROT==
{| class="wikitable" border="1"
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 3-0
| Old FCRAM DMA cutoff size, 0 = no protection.
|-
| style="background: red" | No
| 7-4
| New FCRAM DMA cutoff size, 0 = no protection.
|-
| style="background: green" | Yes
| 8
| AXIWRAM protection, 0 = accessible.
|-
| style="background: red" | No
| 10-9
| QTM DMA cutoff size
|-
| style="background: green" | Yes
| 31-11
| Zeroes
|}
==PDN_TWLMODE_0==
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.
On cold boot this reg is set to 0.
When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].
==CFG11_WIFICNT==
{| class="wikitable" border="1"
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 0
| Enable wifi subsystem
|}
==CFG11_TWLMODE_0==
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.
==PDN_TWLMODE_1==
==CFG11_TWLMODE_1==
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.
==PDN_TWLMODE_2==
==CFG11_TWLMODE_2==
Bitfield.
Bitfield.
==PDN_TWLMODE_HID==
==CFG11_TWLMODE_HID==
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.
==PDN_WIFI?==
==CFG11_WIFIUNK==
{| class="wikitable" border="1"
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 4
| Wifi-related? Set to 1 very early in NWM-module.
|}
==CFG11_TWLAGB_HIDEMU_MASK==
Set bits will use the corresponding values from [[#CFG11_TWLAGB_HIDEMU_PAD|CFG11_TWLAGB_HIDEMU_PAD]] instead of allowing the hardware to read it from [[HID_Registers#HID_PAD|HID_PAD]].
This is set to 0x1FFF (all buttons and the debug key) and [[#CFG11_TWLAGB_HIDEMU_PAD|CFG11_TWLAGB_HIDEMU_PAD]] is set to 0 when the "Close this software and return to HOME Menu?" dialog is shown to prevent the button presses from propagating to the DS/GBA CPU.
==CFG11_TWLAGB_HIDEMU_PAD==
Works the same way as [[HID_Registers#HID_PAD|HID_PAD]], but the values set here are only replaced in the HID_PAD seen by the DS/GBA CPU when the corresponding bits in [[#CFG11_TWLAGB_HIDEMU_MASK|CFG11_TWLAGB_HIDEMU_MASK]] are set.
==PDN_GPU_CNT==
==CFG11_GPU_CNT==
This one seems to control the LCD/GPU/Backlight.
This one seems to control the LCD/GPU/Backlight.
Bit0: Enable GPU registers at 0x10400000+.
Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled).
Bit16: Turn on LCD backlight.
When this is unset VRAM is not accessible and triggers exceptions.
Bits 1..6: other nRESET bits.
Bit16: Enable/Turn on LCD backlight.
==PDN_GPU_CNT2==
PDN uses a 12 Arm11 cycle delay to deassert reset.
==CFG11_GPU_CNT2==
Bit0: Power on GPU?
Bit0: Power on GPU?
==PDN_GPU_CNT3==
==CFG11_GPU_FCRAM_CNT==
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.
Bit1: Enable/disable FCRAM.
Bit2: Enable/disable operation in progress.
==PDN_CODEC==
==CFG11_CODEC==
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.
==PDN_CODEC_CNT==
==CFG11_CODEC_CNT==
This is the power register used for the [[PDN_Services|PDN]] CODEC service.
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.
==PDN_CAMERA_CNT==
==CFG11_CAMERA_CNT==
This is the power register used for the [[PDN_Services|PDN]] camera service.
This is the power register used for the [[CFG11_Services|PDN]] camera service.
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
==CFG11_DSP_CNT==
This is the power register used for the [[CFG11_Services|PDN Services]] DSP service.
bit0: NRESET (active low). Unset to reset/hold reset.
bit1: enable bit.
PDN services holds reset for 0x30 Arm11 cycles.