516
edits
Changes
→CFG11_SOCINFO
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SHAREDWRAM_32K_DATA|PDN_SHAREDWRAM_32K_DATA]]<0-7>
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7>
| 0x10140000
| 0x10140000
| 1*8
| 1*8
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SHAREDWRAM_32K_CODE|PDN_SHAREDWRAM_32K_CODE]]<0-7>
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7>
| 0x10140008
| 0x10140008
| 1*8
| 1*8
| Boot11, Process9, [[DSP Services]]
| Boot11, Process9, [[DSP Services]]
|-
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_NULLPAGE_CNT|CFG11_NULLPAGE_CNT]]
| 0x10140100
| 0x10140100
| 2
| 4
|
|
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_FIQ_MASK|CFG11_FIQ_MASK]]
| 0x10140102
| 0x10140104
| 0x10140104
| 1
| 1
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| Debug related bitfield?
Observed: 0b1100(N3DS)/0b0000(O3DS)
| 0x10140105
| 0x10140105
| 1
| 1
| Kernel11.
|
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_CDMA_CNT|CFG_CDMA_CNT]]
| 0x10140108
| 0x1014010C
| 2
| 2
| TwlBg
| TwlBg
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]
| 0x1014010C
| 0x10140140
| 0x10140140
| 2
| 4
|
| Kernel11
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_WIFI_CNT|PDN_WIFI_CNT]]
| [[#CFG11_WIFICNT|CFG11_WIFICNT]]
| 0x10140180
| 0x10140180
| 1
| 1
| TwlBg
| TwlBg, [[NWM Services]]
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SPI_CNT|PDN_SPI_CNT]]
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]
| 0x101401C0
| 0x101401C0
| 4
| 2
| [[SPI Services]], TwlBg
| [[SPI Services]], TwlBg
|-
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| ?
| 0x10140200
| 0x10140200
| 4
| 4
|
|
|-style="border-top: double"
|-style="border-top: double"
| style="background: red" | No
| style="background: red" | No
| Clock related?
| [[#CFG11_GPU_N3DS_CNT|CFG11_GPU_N3DS_CNT]]
| 0x10140400
| 0x10140400
| 1
| 1
| NewProcess11
| NewKernel11
|-
|-
| style="background: red" | No
| style="background: red" | No
| Clock related?
| [[#CFG11_CDMA_PERIPHERALS|CFG11_CDMA_PERIPHERALS]]
| 0x10140410
| 0x10140410
| 4
| 4
| NewProcess11
| NewKernel11
|-
|-
| style="background: red" | No
| style="background: red" | No
| [[#PDN_BOOTROM_OVERLAY_CNT|PDN_BOOTROM_OVERLAY_CNT]]
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]
| 0x10140420
| 0x10140420
| 4
| 1
| NewProcess11
| NewKernel11
|-
|-
| style="background: red" | No
| style="background: red" | No
| [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]]
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]
| 0x10140424
| 0x10140424
| 4
| 4
| NewProcess11
| NewKernel11
|-
|-
| style="background: red" | No
| style="background: red" | No
| 0x10140428
| 0x10140428
| 4
| 4
|
|
|-style="border-top: double"
|-style="border-top: double"
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_MPCORE_CFG|PDN_MPCORE_CFG]]
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]
| 0x10140FFC
| 0x10140FFC
| 2
| 2
| Boot11, Kernel11
| Boot11, Kernel11
|}
|}
== PDN_SHAREDWRAM_32K_DATA ==
== CFG11_SHAREDWRAM_32K_CODE ==
Used for mapping 32K chunks of shared WRAM for DSP data.
Used for mapping 32K chunks of shared WRAM for DSP data.
|-
|-
| 0-1
| 0-1
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)
|-
|-
| 2-4
| 2-4
|}
|}
== PDN_SHAREDWRAM_32K_CODE ==
== CFG11_SHAREDWRAM_32K_DATA ==
Used for mapping 32K chunks of shared WRAM for DSP data.
Used for mapping 32K chunks of shared WRAM for DSP data.
|-
|-
| 0-1
| 0-1
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)
|-
|-
| 2-4
| 2-4
|}
|}
== PDN_SPI_CNT ==
== CFG11_NULLPAGE_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bit
! Bit
|-
|-
| 0
| 0
| Enable [[SPI Registers]] 0x10160000.
| Trap all ''data'' accesses to physmem addresses 0x0000 to 0x1000
|-
|-
| 2
| 16
| Enable [[SPI Registers]] 0x10143800.
| Unknown
|}
|}
== PDN_BOOTROM_OVERLAY_CNT ==
The reset value of this register is 0x10000.
== CFG11_FIQ_MASK ==
Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)
Reset value: 0xF
== PDN_MPCORE_CFG ==
== CFG11_CDMA_CNT ==
Write 1 to enable, to disable.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| Always set to 1 on both Old3DS and New3DS.
| Enable Microphone DMA (CDMA 0x00)
|-
|-
| 1
| 1
| 3rd ARM11 MPCore available maybe?
| Enable NTRCARD DMA on Arm11 side (CDMA 0x01)
|-
| 2-4
| ?
|-
|-
| 2
| 5
| 4th ARM11 MPCore available maybe?
| WiFi. Enabled during kernel init since 11.4.
|}
|}
== PDN_MPCORE_STATUS ==
== CFG11_SPI_CNT ==
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bit
! Description
! Description
|-
|-
| 0
| 0
| Always set to 1 on both Old3DS and New3DS.
| Enable [[SPI Registers]] 0x10160800.
|-
|-
| 1
| 1
| 3rd ARM11 MPCore powered on maybe?
| Enable [[SPI Registers]] 0x10142800.
|-
|-
| 2
| 2
| 4th ARM11 MPCore powered on maybe?
| Enable [[SPI Registers]] 0x10143800.
|}
|}
== PDN_MPCORE_CNT ==
== CFG11_GPU_N3DS_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bit
! Description
! Description
|-
|-
| 0
| 0
| Power on 3rd ARM11 MPCore maybe?
| Enable N3DS mode? (enables access to the extra N3DS FCRAM banks, etc.)
|-
|-
| 8
| 1
| Power on 4th ARM11 MPCore maybe?
| Texture related? (observing texture glitches when disabling this bit)
|}
|}
== PDN_MPCORE_BOOTCNT<0-3> ==
== CFG11_CDMA_PERIPHERALS ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bit
! Description
! Description
|-
|-
| 0
| 0-17
| Enable bootrom instruction overlay. This bit is only writable for core2 and core3.
| CDMA Peripheral 0x00-0x11 data request target (0=Old CDMA, 1=New CDMA)
|-
|-
| 5
| 18-31
| Always 1?
| Unused
|}
|}
== CFG11_BOOTROM_OVERLAY_CNT ==
Bit0: Enable bootrom overlay functionality.
== CFG11_BOOTROM_OVERLAY_VAL ==
The 32-bit value to overlay data-reads to bootrom with. See [[PDN Registers#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3>.
== CFG11_SOCINFO ==
Read-only register. Identifies the maximum mode-switching capabilities of the SoC.
* CTR: O3DS
* LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below)
* LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode.
==PDN_TWLMODE_0==
{| class="wikitable" border="1"
! Bits
! Description
! Used by
|-
| 0
| CTR mode (1 on all 3DSes)
| Boot11
|-
| 1
| LGR1 (1 on all N3DSes, orginally 2 cores, and 2x clockrate)
| Kernel11
|-
| 2
| LGR2 (1 on all released N3DSes, 4 cores and 3x clockrate)
| Kernel11
|}
==CFG11_GPUPROT==
{| class="wikitable" border="1"
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 3-0
| Old FCRAM DMA cutoff size, 0 = no protection.
|-
| style="background: red" | No
| 7-4
| New FCRAM DMA cutoff size, 0 = no protection.
|-
| style="background: green" | Yes
| 8
| AXIWRAM protection, 0 = accessible.
|-
| style="background: red" | No
| 10-9
| QTM DMA cutoff size
|-
| style="background: green" | Yes
| 31-11
| Zeroes
|}
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.
On cold boot this reg is set to 0.
When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].
==CFG11_WIFICNT==
{| class="wikitable" border="1"
==PDN_CAMERA_CNT==
! Old3DS
! Bits
! Description
|-
| style="background: green" | Yes
| 0
| Enable wifi subsystem
|}