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→CFG9_SDMMCCTL: Oops
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ?
| [[#CFG9_SDMMCCTL|CFG9_SDMMCCTL]]
| 0x10000020
| 0x10000020
| 2
| 2
|
| Process9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
|-
|-
| 0
| 0
| Disables ARM9 [[Memory_layout|bootrom]](+0x8000) when set to 1. Cannot be cleared to 0 once set to 1.
| Disables ARM9 [[Memory_layout|bootrom]](+0x8000) when set to 1, and enables access to [[Memory_layout|FCRAM]]. Cannot be cleared to 0 once set to 1.
| Boot9
| Boot9
|-
|-
|-
|-
| 0
| 0
| Disables ARM11 [[Memory_layout|bootrom]](+0x8000) when set to 1. Cannot be cleared to 0 once set to 1.
| Disables ARM11 [[Memory_layout|bootrom]](+0x8000) when set to 1, and enables access to [[Memory_layout|FCRAM]]. Cannot be cleared to 0 once set to 1.
| Boot9
| Boot9
|-
|-
|-
|-
| 8
| 8
| Enable gamecard eject IRQ, maybe?
| 1 = Switch to [[SPICARD_Registers|SPICARD]] interface (savegames).
| Process9
| Process9
|}
|}
| ?
| ?
| Process9
| Process9
|}
== CFG9_SDMMCCTL ==
This register controls power of multiple ports/controllers and allows to map controller 3 to ARM9 or ARM11. The SD card can be accessed on ARM11 by setting bit 8 and clearing bit 9.
{| class="wikitable" border="1"
! Bit
! Description
! Used by
|-
| 0
| Controller 1/3 port 0 power (SD card) (1=off)
| Process9
|-
| 1
| Controller 1 port 1 power (eMMC) (1=off)
| Process9
|-
| 2
| Controller 2 port 0 power (WiFi SDIO) (1=off)
| Process9
|-
| 3
| Controller 3 port 1 power? Set at cold boot.
| -
|-
| 4-5
| Unused.
| -
|-
| 6
| Wifi port related? Pull up? Set at cold boot.
| -
|-
| 8
| Controller 3 mapping (0=ARM9 0x10007000, 1=ARM11 0x10100000)
| Process9
|-
| 9
| SD card controller select (0=0x10007000/0x10100000, 1=0x10006000)
| Process9
|-
| 10-15
| Unused.
| -
|}
|}