Changes

1,356 bytes added ,  00:14, 3 May 2023
Add info on cart power supply bits
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
| ?
+
| [[#CFG9_XDMA_CNT|CFG9_XDMA_CNT]]
 
| 0x10000008
 
| 0x10000008
 
| 1
 
| 1
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
| ?
+
| [[#CFG9_SDMMCCTL|CFG9_SDMMCCTL]]
 
| 0x10000020
 
| 0x10000020
 
| 2
 
| 2
|
+
| Process9
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
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|-
 
|-
 
| 1
 
| 1
| Disables [[OTP_Registers|OTP area]] when set to 1. On N3DS, also enables access to the extra 128 MB of [[Memory_layout|FCRAM]]. Cannot be cleared to 0 once set to 1.
+
| Disables [[OTP_Registers|OTP area]] when set to 1. Cannot be cleared to 0 once set to 1.
 
| NewKernel9Loader, Process9
 
| NewKernel9Loader, Process9
 
|-
 
|-
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|}
 
|}
   −
== 0x10000008 ==
+
== CFG9_XDMA_CNT ==
 +
 
 +
Write 1 to enable XDMA for the device, 0 to disable. Always enabled for CTRCARD (ids 0 and 1), NTRCARD (id 8), and SHA (id 6 for infifo and 7 for outfifo).
 +
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bit
 
!  Bit
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!  Used by
 
!  Used by
 
|-
 
|-
| 1-0
+
| 0
| ?
+
| SDIO controller 1 (eMMC and usually SD card; XDMA device ID: 2)
 +
|
 +
|-
 +
| 1
 +
| SDIO controller 3 (SD card if configured so; ID: 3)
 
|
 
|
 
|-
 
|-
| 3-2
+
| 2
| AES related? Value 3 written after write to AES_CTL.
+
| AES Input FIFO (ID: 4)
 +
| Boot9, Process9, TwlProcess9
 +
|-
 +
| 3
 +
| AES Output FIFO (ID: 5)
 
| Boot9, Process9, TwlProcess9
 
| Boot9, Process9, TwlProcess9
 
|-
 
|-
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|-
 
|-
 
| 8
 
| 8
| Enable gamecard eject IRQ, maybe?
+
| 1 = Switch to [[SPICARD_Registers|SPICARD]] interface (savegames).
 
| Process9
 
| Process9
 
|}
 
|}
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|-
 
|-
 
| 3-2
 
| 3-2
| ?
+
| Cartridge-slot power supply (0=off, 1=prepare power regulator, 2=enable output, 3=request power down)
 +
| Process9
 +
|}
 +
 
 +
When the power supply is in the "request power down" state, the power bits will be reset to 0=off after some time.
 +
 
 +
== CFG9_SDMMCCTL ==
 +
This register controls power of multiple ports/controllers and allows to map controller 3 to ARM9 or ARM11. The SD card can be accessed on ARM11 by setting bit 8 and clearing bit 9.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bit
 +
!  Description
 +
!  Used by
 +
|-
 +
| 0
 +
| Controller 1/3 port 0 power (SD card) (1=off)
 +
| Process9
 +
|-
 +
| 1
 +
| Controller 1 port 1 power (eMMC) (1=off)
 +
| Process9
 +
|-
 +
| 2
 +
| Controller 2 port 0 power (WiFi SDIO) (1=off)
 +
| Process9
 +
|-
 +
| 3
 +
| Controller 3 port 1 power? Set at cold boot.
 +
| -
 +
|-
 +
| 4-5
 +
| Unused.
 +
| -
 +
|-
 +
| 6
 +
| Wifi port related? Pull up? Set at cold boot.
 +
| -
 +
|-
 +
| 8
 +
| Controller 3 mapping (0=ARM9 0x10007000, 1=ARM11 0x10100000)
 +
| Process9
 +
|-
 +
| 9
 +
| SD card controller select (0=0x10007000/0x10100000, 1=0x10006000)
 
| Process9
 
| Process9
 +
|-
 +
| 10-15
 +
| Unused.
 +
| -
 
|}
 
|}
  
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