Line 1: |
Line 1: |
| = Registers = | | = Registers = |
| + | |
| + | == GPIO == |
| + | |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Name | | ! Name |
Line 35: |
Line 38: |
| | 2 | | | 2 |
| | 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000 | | | 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000 |
| + | |- |
| + | | ? |
| + | | [[#0x10147026|0x10147026]] |
| + | | 2 |
| + | | ? |
| |- | | |- |
| | GPIO_DATA4 | | | GPIO_DATA4 |
Line 41: |
Line 49: |
| | 0x40000 | | | 0x40000 |
| |} | | |} |
| + | |
| + | == Legacy RTC == |
| + | {| class="wikitable" border="1" |
| + | ! Name |
| + | ! Address |
| + | ! Width |
| + | ! Description |
| + | |- |
| + | | [[#RTC_CNT_(0x10147100)|RTC_CNT]] |
| + | | 0x10147100 |
| + | | 2 |
| + | | Control register |
| + | |- |
| + | | RTC_REG_STAT1 |
| + | | 0x10147110 |
| + | | 1 |
| + | | Rtc status register 1 (command 0). Bitswapped |
| + | |- |
| + | | RTC_REG_STAT2 |
| + | | 0x10147111 |
| + | | 1 |
| + | | Rtc status register 2 (command 1). Bitswapped |
| + | |- |
| + | | RTC_REG_CLKADJ |
| + | | 0x10147112 |
| + | | 1 |
| + | | Rtc clock adjustment register (command 6). Bitswapped |
| + | |- |
| + | | RTC_REG_FREE |
| + | | 0x10147113 |
| + | | 1 |
| + | | The free general purpose rtc register (command 7). Bitswapped |
| + | |- |
| + | | RTC_REG_TIME1 |
| + | | 0x10147120 |
| + | | 4 |
| + | | Byte-wise bit-swapped (bit7 is bit0, etc.) BCD RTC (byte0 = seconds, byte1 = minutes, byte2 = hours, byte3 = day of week) |
| + | |- |
| + | | RTC_REG_TIME2 |
| + | | 0x10147124 |
| + | | 4 (3?) |
| + | | Day, month and year all byte-wise bit-swapped |
| + | |- |
| + | | RTC_REG_ALRMTIM1 |
| + | | 0x10147130 |
| + | | 4 (3?) |
| + | | Rtc alarm time register 1 (command 4). Byte-wise bit-swapped |
| + | |- |
| + | | RTC_REG_ALRMTIM2 |
| + | | 0x10147134 |
| + | | 4 (3?) |
| + | | Rtc alarm time register 2 (command 5). Byte-wise bit-swapped |
| + | |- |
| + | | RTC_REG_COUNT |
| + | | 0x10147140 |
| + | | 4 (3?) |
| + | | Rtc dsi counter register (ex command 0). Byte-wise bit-swapped |
| + | |- |
| + | | RTC_REG_FOUT1 |
| + | | 0x10147150 |
| + | | 1 |
| + | | Rtc dsi fout register 1 (ex command 1). Bitswapped |
| + | |- |
| + | | RTC_REG_FOUT2 |
| + | | 0x10147151 |
| + | | 1 |
| + | | Rtc dsi fout register 2 (ex command 2). Bitswapped |
| + | |- |
| + | | RTC_REG_ALRMDAT1 |
| + | | 0x10147160 |
| + | | 4 (3?) |
| + | | Rtc dsi alarm date register 1 (ex command 4). Byte-wise bit-swapped |
| + | |- |
| + | | RTC_REG_ALRMDAT2 |
| + | | 0x10147164 |
| + | | 4 (3?) |
| + | | Rtc dsi alarm date register 2 (ex command 5). Byte-wise bit-swapped |
| + | |- |
| + | |} |
| + | |
| + | = Descriptions = |
| | | |
| == 0x10147010 == | | == 0x10147010 == |
Line 53: |
Line 142: |
| | 25 | | | 25 |
| | Enable/disable? GPIO interrupt 0x66 (bitmask 0x10) | | | Enable/disable? GPIO interrupt 0x66 (bitmask 0x10) |
| + | |} |
| + | |
| + | == 0x10147026 == |
| + | |
| + | {| class="wikitable" border="1" |
| + | ! Bit |
| + | ! Description |
| + | |- |
| + | | 0-8 |
| + | | ? |
| + | |- |
| + | | 9 |
| + | | Enable/disable interrupt 0x71. |
| + | |- |
| + | | 10-15 |
| + | | ? |
| |} | | |} |
| | | |
Line 64: |
Line 169: |
| | 0-2 | | | 0-2 |
| | Used for GPIO [[GPIO_Services|bitmask]] 0x7. | | | Used for GPIO [[GPIO_Services|bitmask]] 0x7. |
| + | |- |
| + | | 1 |
| + | | DS EXTKEYIN Pen down (0 = touching, 1 = not touching) |
| |- | | |- |
| | 3 | | | 3 |
Line 121: |
Line 229: |
| | 1-15 | | | 1-15 |
| | Unused by GPIO-sysmodule and TwlBg. | | | Unused by GPIO-sysmodule and TwlBg. |
| + | |} |
| + | |
| + | == Legacy RTC == |
| + | === RTC_CNT (0x10147100) === |
| + | {| class="wikitable" border="1" |
| + | ! Bit |
| + | ! Description |
| + | |- |
| + | | 0 |
| + | | Latch STAT1 |
| + | |- |
| + | | 1 |
| + | | Latch STAT2 |
| + | |- |
| + | | 2 |
| + | | Latch CLKADJ |
| + | |- |
| + | | 3 |
| + | | Latch FREE |
| + | |- |
| + | | 4 |
| + | | Latch TIME |
| + | |- |
| + | | 5 |
| + | | Latch ALRMTIM1 |
| + | |- |
| + | | 6 |
| + | | Latch ALRMTIM2 |
| + | |- |
| + | | 7 |
| + | | Latch COUNT |
| + | |- |
| + | | 8 |
| + | | Latch FOUT1 |
| + | |- |
| + | | 9 |
| + | | Latch FOUT2 |
| + | |- |
| + | | 10 |
| + | | Latch ALRMDAT1 |
| + | |- |
| + | | 11 |
| + | | Latch ALRMDAT2 |
| + | |- |
| + | | 12 |
| + | | ARM7 Busy? This may be chipselect |
| + | |- |
| + | | 13 |
| + | | ARM7 write command received? (writing 1 clears it seems) |
| + | |- |
| + | | 14 |
| + | | ARM7 read command recieved? (writing 1 clears it seems) |
| + | |- |
| + | | 15 |
| + | | DS SIO SI pin (rtc irq pin) |
| |} | | |} |
| | | |