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Line 4,138: + + − − These registers map components of the corresponding vertex shader output register to specific fixed-function semantics. Line 4,108:
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Line 4,735: − + − === GPUREG_LIGHTING_ENABLE0 ===+ − {| class="wikitable" border="1"+ − ! Bits − ! Description − |- − | 0 − | unsigned, Enabled (0 = disabled, 1 = enabled) − |} − − === GPUREG_TEXUNIT3_PROCTEX0 === − + − + + + − + − + + + − + − + + + − + − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Line 4,689:
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Line 6,253: − Color components are laid out in reverse byte order in memory, with the most significant bits used first. Line 6,014:
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Line 6,501: + + − + − This register is set to 0 when fragment lighting is disabled, and to 1 when it is enabled.+ + + + + + + + + + + + + − === GPUREG_LIGHTING_ENABLE1 ===+ − This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.+ − === GPUREG_LIGHTING_CONFIG0 === Line 6,213:
Line 6,531: − + − + − + − + − + − + + + + + + + + + + − + − + − + − + − | 16+ − | unsigned, "Shadow primary", 0=disabled, 1=enabled+ − |- − | 17 − | unsigned, "Shadow secondary", 0=disabled, 1=enabled − |- − | 18 − | unsigned, "Invert shadow", 0=disabled, 1=enabled − |- − | 19 − | unsigned, "Shadow alpha", 0=disabled, 1=enabled − |- − − | Unknown, set to 0 − |- − | 22-23 − | unsigned, "Bump selector", texture unit for bumpmapping − |- − | 24-25 − | unsigned, "Shadow selector", texture unit for shadow mapping − |- − | 26 − | Unknown, set to 0 − |- − | 27 − − |- − | 28-29 − | unsigned, "Bump mode", "Light env texy usage" (see below) − |- − | 30 − | unsigned, "Bump renorm", 0=enabled, 1=disabled − |- − | 31 − | Unknown, set to 1 − Fresnel selector constants:+ + + − + − + − + − + − + − + − | SEC_ALPHA_FRESNEL+ − |- − − | PRI_SEC_ALPHA_FRESNEL − The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If lut_RR is enabled but not lut_RG or lut_RB, the output of lut_RR is used for the three components; Red, Green and Blue.+ − Light env config constants:+ − + − ! Available LUTs − + − + − | lut_D0, lut_RR, lut_SP, lut_DA − + − + − + − |-+ − + − | LIGHT_ENV_LAYER_CONFIG2+ − | lut_D0, lut_D1, lut_RR, lut_DA+ + + + + − + − + − + + + + + + + + + − + − + − | All except for lut_FR − + − | LIGHT_ENV_LAYER_CONFIG5+ − | All except for lut_D1 − |- − − | LIGHT_ENV_LAYER_CONFIG6 − | All except for lut_RB and lut_RG − |- − | 8 (sic) − | LIGHT_ENV_LAYER_CONFIG7 − | All − Bump mode constants:+ + + − + − + − | BUMP_NOT_USED+ − |- − − | BUMP_AS_BUMP − |- − | 2 − | BUMP_AS_TANG − Bit 30 is set when bump mode is not zero.+ − + Line 6,351:
Line 6,640: − + − + − + − + + + + + + + + + + − + − + + + + + + + + + + − + − + + + + + + + + + + − + − + − + − + − + − + + + + + + + + + + − + − + + + + + + + + + + − + − + − + − + − + − + − + − | unsigned, Disable bit for frag light source 5 spot+ − |- − − | unsigned, Disable bit for frag light source 6 spot − |- − | 15 − | unsigned, Disable bit for frag light source 7 spot − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + + + + + + + + + + − + − + − + − + − + − + − + − + − |- − | 30 − | unsigned, Disable bit for frag light source 6 distance attenuation − |- − | 31 − | unsigned, Disable bit for frag light source 7 distance attenuation − === GPUREG_LIGHTING_NUM_LIGHTS ===+ − − − === GPUREG_LIGHTING_LIGHT_PERMUTATION ===+ − + + − + − + + − + − + + − + − + + − + − + + − + − + + − + − + + − + − + + − + − + + − === GPUREG_LIGHTING_LUTINPUT_SELECT ===+ − + − + − + − + − + − + − + − |- − | 12-15 − | unsigned, Input selector for lut_FR − |- − | 16-19 − | unsigned, Input selector for lut_RB − |- − | 20-23 − | unsigned, Input selector for lut_RG − |- − | 24-27 − | unsigned, Input selector for lut_RR − Input selector values:+ − + − + − + − + − + − + − + − + − + − === GPUREG_LIGHTING_LUTINPUT_ABS ===+ − − {| class="wikitable" border="1" − ! Bits − ! Description − + − + − + − + − + + + + + + + + + + − + + + + + + + + + + − + + + + + + + + + + − + + + + + + + − + + + + + + + + + + + + + + + + + + + − + − + Line 6,571:
Line 6,944: − + − + − | 4-7+ − | unsigned, Scaler selector for lut_D1+ − |- − − | unsigned, Scaler selector for lut_SP − |- − | 12-15 − − |- − | 16-19 − | unsigned, Scaler selector for lut_RB − |- − | 20-23 − | unsigned, Scaler selector for lut_RG − |- − | 24-27 − | unsigned, Scaler selector for lut_RR − Scaler selector values:+ + + Line 6,600:
Line 6,960: − + − + + + + − + − + − + − + − + + + + − + − + − This register controls the scaling that is applied to the output of a LUT.+ − === GPUREG_LIGHTING_LUT_INDEX ===+ − − This register controls which LUT and what offset into it the LUT_DATA register writes to. − − − + − + − |- − | 8-10 − | unsigned, LUT ID (context=0) or Light ID (context=1,2) − |- − | 11-12 − | unsigned, Context ID − LUT ID values:+ − {| class="wikitable" border="1"+ − ! Value − ! Description − |- − | 0 − | lut_D0 − |- − | 1 − | lut_D1 − |- − | 3 − | lut_FR − |- − | 4 − | lut_RB − |- − | 5 − | lut_RG − |- − | 6 − | lut_RR − |} − − Context ID values: − + − + − | unsigned, LUTs common to all lights - writes to the LUT selected by the ID+ − |- − | 1 − | unsigned, lut_SP - writes to the LUT specific to the selected light − − | 2 − | unsigned, lut_DA - writes to the LUT specific to the selected light − − === GPUREG_LIGHTING_LUT_DATA === Line 6,685:
Line 7,010: − lut_DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.+ Line 6,694:
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Line 7,061: − + − + + + + − + − + − + − + − + − + − |} − − === GPUREG_LIGHTx_XY === − − {| class="wikitable" border="1" − ! Bits − ! Description − + − + − + − + − These registers (along with _Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.+ − === GPUREG_LIGHTx_Z ===+ − + − + − + + + + + + + + + + + + + + + + − These registers (along with _XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.+ − − Line 6,770:
Line 7,116: − + − + + + + − + − + + + + + + + + + + + + + − These registers (along with _Z) represent the spot direction (unitary) vector of the corresponding light.+ − === GPUREG_LIGHTx_SPOTDIR_Z ===+ − + − + − + + + + + + + + + + + + + + + + − These registers (along with _XY) represent the spot direction (unitary) vector of the corresponding light.+ − − − − These registers contain the distance attenuation bias value (float20 = 1.7.12) of the corresponding light. The attenuation factor is lut_DA(clip(bias + scale*distance, 0.0, 1.0)). − − === GPUREG_LIGHTx_ATTENUATION_SCALE === − − These registers contain the distance attenuation scale value (float20 = 1.7.12) of the corresponding light. The attenuation factor is lut_DA(clip(bias + scale*distance, 0.0, 1.0)). − − === GPUREG_LIGHTx_AMBIENT === − − These registers contain the ambient color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_ambient*lightX_ambient. − − === GPUREG_LIGHTx_DIFFUSE === − − These registers contain the diffuse color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_diffuse*lightX_diffuse. − − === GPUREG_LIGHTx_SPECULAR0 === − − These registers contain the specular0 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular0*lightX_specular0. − − === GPUREG_LIGHTx_SPECULAR1 === − − These registers contain the specular1 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular1*lightX_specular1. − − == Geometry pipeline registers == − − === GPUREG_GEOSTAGE_CONFIG === Line 6,823:
Line 7,171: − + − + − + − + − + − + − + − + − + − + − + − + − This register configures the geometry stage of the GPU pipeline.+ − + − === GPUREG_FIXEDATTRIB_INDEX ===+ − + − See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info. − − {| class="wikitable" border="1" − ! Bits − ! Description − + − + − === GPUREG_FIXEDATTRIB_DATA ===+ − Accepts a packed 4-tuple of float24 values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].+ − If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.+ − − Line 6,865:
Line 7,206: − + − + − == Geometry shader registers ==+ − + Line 6,877:
Line 7,218: − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − | unsigned, Value of geometry shader unit's b15 boolean register. (0=true, 1=false)+ − |- − | 16-31 − − + − === GPUREG_GSH_INTUNIFORM_I0 ===+ − + − + − + − + − + − + − + − + − + − This register is used to set the geometry shader's i0 integer register.+ − − === GPUREG_GSH_INTUNIFORM_I1 === − + − + − + − + − + − + − + − + − + − This register is used to set the geometry shader's i1 integer register.+ − − Line 6,979:
Line 7,313: − + − + − + − + − + − + − |- − | 24-31 − | unsigned, Value for geometry shader's i2.w − |} − − This register is used to set the geometry shader's i2 integer register. − − === GPUREG_GSH_INTUNIFORM_I3 === − − {| class="wikitable" border="1" − ! Bits − ! Description − + − + − + − + − + − + − + − + − |} − − This register is used to set the geometry shader's i3 integer register. − − === GPUREG_GSH_INPUTBUFFER_CONFIG === − − {| class="wikitable" border="1" − ! Bits − ! Description − + − + − + − + − + − + − + + − + Line 7,040:
Line 7,354: − + − + − |- − | 16-31 − | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang − + − + Line 7,056:
Line 7,367: − + − + − + − + − + − + − + − + − + − For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute. − === GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===+ − + − + − + + + + − + − + − + − + − + − + − + − + − + − + − + − + − + − | unsigned, Index of geometry shader input register which the 16th attribute will be stored in.+ − − − This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. − For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute. − − === GPUREG_GSH_OUTMAP_MASK === − − {| class="wikitable" border="1" − ! Bits − ! Description − + − + − + − + − + − + − + − + − + − + − + − + − + − + − This register toggles the geometry shader unit's output registers.+ − − Line 7,153:
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Line 7,499: − + − + − * In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :+ − ** first word : ZZWWWWWW+ − ** second word : YYYYZZZZ+ − ** third word : XXXXXXYY+ − * In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.+ + + + + + + + + + + + + + + + + + − + Line 7,198:
Line 7,533: − + − + − + + + + + + + + + + + − NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.+ − + Line 7,213:
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Line 7,605: − + − − + − + − + − + − + − − + − + − + − + − + − − + − + − + − | unsigned, Value of vertex shader unit's b8 boolean register. (0=true, 1=false)+ − |- − − | unsigned, Value of vertex shader unit's b9 boolean register. (0=true, 1=false) − |- − | 10 − | unsigned, Value of vertex shader unit's b10 boolean register. (0=true, 1=false) − |- − | 11 − | unsigned, Value of vertex shader unit's b11 boolean register. (0=true, 1=false) − |- − | 12 − | unsigned, Value of vertex shader unit's b12 boolean register. (0=true, 1=false) − |- − | 13 − | unsigned, Value of vertex shader unit's b13 boolean register. (0=true, 1=false) − |- − | 14 − | unsigned, Value of vertex shader unit's b14 boolean register. (0=true, 1=false) − |- − | 15 − | unsigned, Value of vertex shader unit's b15 boolean register. (0=true, 1=false) − |- − | 16-31 − | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang − This register is used to set the vertex shader unit's boolean registers.+ − + Line 7,310:
Line 7,638: − + − + − |- − | 8-15 − | unsigned, Value for vertex shader's i0.y − |- − | 16-23 − | unsigned, Value for vertex shader's i0.z − |- − | 24-31 − | unsigned, Value for vertex shader's i0.w − + − + Line 7,331:
Line 7,650: − + − + − |- − | 8-15 − | unsigned, Value for vertex shader's i1.y − |- − | 16-23 − | unsigned, Value for vertex shader's i1.z − |- − | 24-31 − | unsigned, Value for vertex shader's i1.w − + − + Line 7,352:
Line 7,662: − + − + − |- − | 8-15 − | unsigned, Value for vertex shader's i2.y − |- − | 16-23 − | unsigned, Value for vertex shader's i2.z − |- − | 24-31 − | unsigned, Value for vertex shader's i2.w − + − + Line 7,373:
Line 7,674: − + − + − |- − | 8-15 − | unsigned, Value for vertex shader's i3.y − |- − | 16-23 − | unsigned, Value for vertex shader's i3.z − |- − | 24-31 − | unsigned, Value for vertex shader's i3.w − + − + Line 7,394:
Line 7,686: − + − + − |- − | 8-23 − | Unknown. These bits typically aren't updated by games. − |- − | 24-31 − | Unknown. This is typically set to 0xA for vertex shaders. − + − + Line 7,412:
Line 7,698: − + − + − |- − | 16-31 − | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang − + − + Line 7,428:
Line 7,711: − + + + + + + + + + + − + − + + + + + + + + + + − + − + − + − + + + + + + + + + + − + − + − |- − | 20-23 − | unsigned, Index of vertex shader input register which the 6th attribute will be stored in. − |- − | 24-27 − | unsigned, Index of vertex shader input register which the 7th attribute will be stored in. − |- − | 28-31 − | unsigned, Index of vertex shader input register which the 8th attribute will be stored in. − + − For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute. − + Line 7,462:
Line 7,762: − + − |- − | 4-7 − | unsigned, Index of vertex shader input register which the 10th attribute will be stored in. − |- − | 8-11 − | unsigned, Index of vertex shader input register which the 11th attribute will be stored in. − |- − | 12-15 − | unsigned, Index of vertex shader input register which the 12th attribute will be stored in. − |- − | 16-19 − | unsigned, Index of vertex shader input register which the 13th attribute will be stored in. − |- − | 20-23 − | unsigned, Index of vertex shader input register which the 14th attribute will be stored in. − |- − | 24-27 − | unsigned, Index of vertex shader input register which the 15th attribute will be stored in. − |- − | 28-31 − | unsigned, Index of vertex shader input register which the 16th attribute will be stored in. − + − For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute. − + Line 7,495:
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Line 8,172: − + − + − − * In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes : − ** first word : ZZWWWWWW − ** second word : YYYYZZZZ − ** third word : XXXXXXYY − * In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order. − + Line 7,598:
Line 8,184: − + − + − − NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095. − + Line 7,612:
Line 8,196: − + − + − − === GPUREG_VSH_OPDESCS_CONFIG === − − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0-6 − | unsigned, Target vertex shader operand descriptor offset for data transfer. − |} − − This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written. − − === GPUREG_VSH_OPDESCS_DATA === − − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0-31 − | Vertex shader operand descriptor data. − |} − − This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register. − − [[Category:GPU]]
→Command Header: Size field is 8-bit, not 11-bit (tested on hardware)
[[Category:GFX]]
[[Category:GPU]]
== Overview ==
== Overview ==
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.
=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-27
| Number of extra parameters (may be zero)
|-
| 28-30
| Unused
|-
| 31
| Consecutive writing mode
|}
=== Parameter masking ===
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.
=== Types ===
=== Types ===
There are three main types of registers :
There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])
=== Aliases ===
=== Aliases ===
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]
=== Data Types ===
=== Data Types ===
|-
|-
| 0203
| 0203
| [[#GPUREG_ATTRIBBUFFER0_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
|-
| 0204
| 0204
| [[#GPUREG_ATTRIBBUFFER0_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
|-
| 0205
| 0205
| [[#GPUREG_ATTRIBBUFFER0_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
|-
| 0206
| 0206
| [[#GPUREG_ATTRIBBUFFER1_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|
|
|-
|-
| 0207
| 0207
| [[#GPUREG_ATTRIBBUFFER1_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|
|
|-
|-
| 0208
| 0208
| [[#GPUREG_ATTRIBBUFFER1_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|
|
|-
|-
| 0209
| 0209
| [[#GPUREG_ATTRIBBUFFER2_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|
|
|-
|-
| 020A
| 020A
| [[#GPUREG_ATTRIBBUFFER2_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|
|
|-
|-
| 020B
| 020B
| [[#GPUREG_ATTRIBBUFFER2_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|
|
|-
|-
| 020C
| 020C
| [[#GPUREG_ATTRIBBUFFER3_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|
|
|-
|-
| 020D
| 020D
| [[#GPUREG_ATTRIBBUFFER3_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|
|
|-
|-
| 020E
| 020E
| [[#GPUREG_ATTRIBBUFFER3_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|
|
|-
|-
| 020F
| 020F
| [[#GPUREG_ATTRIBBUFFER4_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|
|
|-
|-
| 0210
| 0210
| [[#GPUREG_ATTRIBBUFFER4_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|
|
|-
|-
| 0211
| 0211
| [[#GPUREG_ATTRIBBUFFER4_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|
|
|-
|-
| 0212
| 0212
| [[#GPUREG_ATTRIBBUFFER5_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|
|
|-
|-
| 0213
| 0213
| [[#GPUREG_ATTRIBBUFFER5_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|
|
|-
|-
| 0214
| 0214
| [[#GPUREG_ATTRIBBUFFER5_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|
|
|-
|-
| 0215
| 0215
| [[#GPUREG_ATTRIBBUFFER6_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|
|
|-
|-
| 0216
| 0216
| [[#GPUREG_ATTRIBBUFFER6_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|
|
|-
|-
| 0217
| 0217
| [[#GPUREG_ATTRIBBUFFER6_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|
|
|-
|-
| 0218
| 0218
| [[#GPUREG_ATTRIBBUFFER7_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|
|
|-
|-
| 0219
| 0219
| [[#GPUREG_ATTRIBBUFFER7_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|
|
|-
|-
| 021A
| 021A
| [[#GPUREG_ATTRIBBUFFER7_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|
|
|-
|-
| 021B
| 021B
| [[#GPUREG_ATTRIBBUFFER8_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|
|
|-
|-
| 021C
| 021C
| [[#GPUREG_ATTRIBBUFFER8_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|
|
|-
|-
| 021D
| 021D
| [[#GPUREG_ATTRIBBUFFER8_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|
|
|-
|-
| 021E
| 021E
| [[#GPUREG_ATTRIBBUFFER9_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|
|
|-
|-
| 021F
| 021F
| [[#GPUREG_ATTRIBBUFFER9_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|
|
|-
|-
| 0220
| 0220
| [[#GPUREG_ATTRIBBUFFER9_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|
|
|-
|-
| 0221
| 0221
| [[#GPUREG_ATTRIBBUFFER10_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|
|
|-
|-
| 0222
| 0222
| [[#GPUREG_ATTRIBBUFFER10_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|
|
|-
|-
| 0223
| 0223
| [[#GPUREG_ATTRIBBUFFER10_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|
|
|-
|-
| 0224
| 0224
| [[#GPUREG_ATTRIBBUFFER11_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|
|
|-
|-
| 0225
| 0225
| [[#GPUREG_ATTRIBBUFFER11_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|
|
|-
|-
| 0226
| 0226
| [[#GPUREG_ATTRIBBUFFER11_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|
|
|-
|-
| 0233
| 0233
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
|-
| 0234
| 0234
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
|-
| 0235
| 0235
| [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
|-
| 0280
| 0280
| [[#GPUREG_GSH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|
|PICA_REG_GS_BOOL
|PICA_REG_GS_BOOL
|-
|-
| 0281
| 0281
| [[#GPUREG_GSH_INTUNIFORM_I0|GPUREG_GSH_INTUNIFORM_I0]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|
|PICA_REG_GS_INT0
|PICA_REG_GS_INT0
|-
|-
| 0282
| 0282
| [[#GPUREG_GSH_INTUNIFORM_I1|GPUREG_GSH_INTUNIFORM_I1]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|
|PICA_REG_GS_INT1
|PICA_REG_GS_INT1
|-
|-
| 0283
| 0283
| [[#GPUREG_GSH_INTUNIFORM_I2|GPUREG_GSH_INTUNIFORM_I2]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|
|PICA_REG_GS_INT2
|PICA_REG_GS_INT2
|-
|-
| 0284
| 0284
| [[#GPUREG_GSH_INTUNIFORM_I3|GPUREG_GSH_INTUNIFORM_I3]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|
|PICA_REG_GS_INT3
|PICA_REG_GS_INT3
|-
|-
| 0289
| 0289
| [[#GPUREG_GSH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|
|PICA_REG_GS_ATTR_NUM
|PICA_REG_GS_ATTR_NUM
|-
|-
| 028A
| 028A
| [[#GPUREG_GSH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|
|PICA_REG_GS_START_ADDR
|PICA_REG_GS_START_ADDR
|-
|-
| 028B
| 028B
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
|-
| 028C
| 028C
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
|-
| 028D
| 028D
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|
|PICA_REG_GS_OUT_REG_MASK
|PICA_REG_GS_OUT_REG_MASK
|-
|-
| 028F
| 028F
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|
|PICA_REG_GS_PROG_RENEWAL_END
|PICA_REG_GS_PROG_RENEWAL_END
|-
|-
| 0290
| 0290
| [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|
|PICA_REG_GS_FLOAT_ADDR
|PICA_REG_GS_FLOAT_ADDR
|-
|-
| 0291
| 0291
| [[#GPUREG_GSH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|
|PICA_REG_GS_FLOAT_DATA1
|PICA_REG_GS_FLOAT_DATA0
|-
|-
| 0292
| 0292
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|
|PICA_REG_GS_FLOAT_DATA2
|PICA_REG_GS_FLOAT_DATA1
|-
|-
| 0293
| 0293
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|
|PICA_REG_GS_FLOAT_DATA3
|PICA_REG_GS_FLOAT_DATA2
|-
|-
| 0294
| 0294
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|
|PICA_REG_GS_FLOAT_DATA4
|PICA_REG_GS_FLOAT_DATA3
|-
|-
| 0295
| 0295
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|
|PICA_REG_GS_FLOAT_DATA5
|PICA_REG_GS_FLOAT_DATA4
|-
|-
| 0296
| 0296
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|
|PICA_REG_GS_FLOAT_DATA6
|PICA_REG_GS_FLOAT_DATA5
|-
|-
| 0297
| 0297
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|
|PICA_REG_GS_FLOAT_DATA7
|PICA_REG_GS_FLOAT_DATA6
|-
|-
| 0298
| 0298
| [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|
|PICA_REG_GS_FLOAT_DATA8
|PICA_REG_GS_FLOAT_DATA7
|-
|-
| 0299
| 0299
|-
|-
| 029B
| 029B
| [[#GPUREG_GSH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
| ?
|PICA_REG_GS_PROG_ADDR
|PICA_REG_GS_PROG_ADDR
|-
|-
| 029C
| 029C
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|
|PICA_REG_GS_PROG_DATA0
|PICA_REG_GS_PROG_DATA0
|-
|-
| 029D
| 029D
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|
|PICA_REG_GS_PROG_DATA1
|PICA_REG_GS_PROG_DATA1
|-
|-
| 029E
| 029E
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|
|PICA_REG_GS_PROG_DATA2
|PICA_REG_GS_PROG_DATA2
|-
|-
| 029F
| 029F
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|
|PICA_REG_GS_PROG_DATA3
|PICA_REG_GS_PROG_DATA3
|-
|-
| 02A0
| 02A0
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|
|PICA_REG_GS_PROG_DATA4
|PICA_REG_GS_PROG_DATA4
|-
|-
| 02A1
| 02A1
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|
|PICA_REG_GS_PROG_DATA5
|PICA_REG_GS_PROG_DATA5
|-
|-
| 02A2
| 02A2
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|
|PICA_REG_GS_PROG_DATA6
|PICA_REG_GS_PROG_DATA6
|-
|-
| 02A3
| 02A3
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|
|PICA_REG_GS_PROG_DATA7
|PICA_REG_GS_PROG_DATA7
|-
|-
| 02A5
| 02A5
| [[#GPUREG_GSH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
|-
| 02A6
| 02A6
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
|-
| 02A7
| 02A7
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
|-
| 02A8
| 02A8
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
|-
| 02A9
| 02A9
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
|-
| 02AA
| 02AA
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
|-
| 02AB
| 02AB
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
|-
| 02AC
| 02AC
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
|-
| 02AD
| 02AD
| [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
|-
| 02B0
| 02B0
| [[#GPUREG_VSH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|
|PICA_REG_VS_BOOL
|PICA_REG_VS_BOOL
|-
|-
| 02B1
| 02B1
| [[#GPUREG_VSH_INTUNIFORM_I0|GPUREG_VSH_INTUNIFORM_I0]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|
|PICA_REG_VS_INT0
|PICA_REG_VS_INT0
|-
|-
| 02B2
| 02B2
| [[#GPUREG_VSH_INTUNIFORM_I1|GPUREG_VSH_INTUNIFORM_I1]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|
|PICA_REG_VS_INT1
|PICA_REG_VS_INT1
|-
|-
| 02B3
| 02B3
| [[#GPUREG_VSH_INTUNIFORM_I2|GPUREG_VSH_INTUNIFORM_I2]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|
|PICA_REG_VS_INT2
|PICA_REG_VS_INT2
|-
|-
| 02B4
| 02B4
| [[#GPUREG_VSH_INTUNIFORM_I3|GPUREG_VSH_INTUNIFORM_I3]]
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|
|PICA_REG_VS_INT3
|PICA_REG_VS_INT3
|-
|-
| 02B9
| 02B9
| [[#GPUREG_VSH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|
|PICA_REG_VS_ATTR_NUM0
|PICA_REG_VS_ATTR_NUM0
|-
|-
| 02BA
| 02BA
| [[#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|
|PICA_REG_VS_START_ADDR
|PICA_REG_VS_START_ADDR
|-
|-
| 02BB
| 02BB
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
|-
| 02BC
| 02BC
| [[#GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
|-
| 02BD
| 02BD
| [[#GPUREG_VSH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|
|PICA_REG_VS_OUT_REG_MASK
|PICA_REG_VS_OUT_REG_MASK
|-
|-
| 02BF
| 02BF
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|
|PICA_REG_VS_PROG_RENEWAL_END
|PICA_REG_VS_PROG_RENEWAL_END
|-
|-
| 02C0
| 02C0
| [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|
|PICA_REG_VS_FLOAT_ADDR
|PICA_REG_VS_FLOAT_ADDR
|-
|-
| 02C1
| 02C1
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|
|PICA_REG_VS_FLOAT_DATA1
|PICA_REG_VS_FLOAT_DATA0
|-
|-
| 02C2
| 02C2
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|
|PICA_REG_VS_FLOAT_DATA2
|PICA_REG_VS_FLOAT_DATA1
|-
|-
| 02C3
| 02C3
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|
|PICA_REG_VS_FLOAT_DATA3
|PICA_REG_VS_FLOAT_DATA2
|-
|-
| 02C4
| 02C4
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|
|PICA_REG_VS_FLOAT_DATA4
|PICA_REG_VS_FLOAT_DATA3
|-
|-
| 02C5
| 02C5
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|
|PICA_REG_VS_FLOAT_DATA5
|PICA_REG_VS_FLOAT_DATA4
|-
|-
| 02C6
| 02C6
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|
|PICA_REG_VS_FLOAT_DATA6
|PICA_REG_VS_FLOAT_DATA5
|-
|-
| 02C7
| 02C7
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|
|PICA_REG_VS_FLOAT_DATA7
|PICA_REG_VS_FLOAT_DATA6
|-
|-
| 02C8
| 02C8
| [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|
|PICA_REG_VS_FLOAT_DATA8
|PICA_REG_VS_FLOAT_DATA7
|-
|-
| 02C9
| 02C9
|-
|-
| 02CB
| 02CB
| [[#GPUREG_VSH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
| ?
|PICA_REG_VS_PROG_ADDR
|PICA_REG_VS_PROG_ADDR
|-
|-
| 02CC
| 02CC
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|
|PICA_REG_VS_PROG_DATA0
|PICA_REG_VS_PROG_DATA0
|-
|-
| 02CD
| 02CD
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|
|PICA_REG_VS_PROG_DATA1
|PICA_REG_VS_PROG_DATA1
|-
|-
| 02CE
| 02CE
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|
|PICA_REG_VS_PROG_DATA2
|PICA_REG_VS_PROG_DATA2
|-
|-
| 02CF
| 02CF
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|
|PICA_REG_VS_PROG_DATA3
|PICA_REG_VS_PROG_DATA3
|-
|-
| 02D0
| 02D0
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|
|PICA_REG_VS_PROG_DATA4
|PICA_REG_VS_PROG_DATA4
|-
|-
| 02D1
| 02D1
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|
|PICA_REG_VS_PROG_DATA5
|PICA_REG_VS_PROG_DATA5
|-
|-
| 02D2
| 02D2
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|
|PICA_REG_VS_PROG_DATA6
|PICA_REG_VS_PROG_DATA6
|-
|-
| 02D3
| 02D3
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|
|PICA_REG_VS_PROG_DATA7
|PICA_REG_VS_PROG_DATA7
|-
|-
| 02D5
| 02D5
| [[#GPUREG_VSH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
|-
| 02D6
| 02D6
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
|-
| 02D7
| 02D7
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
|-
| 02D8
| 02D8
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
|-
| 02D9
| 02D9
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
|-
| 02DA
| 02DA
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
|-
| 02DB
| 02DB
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
|-
| 02DC
| 02DC
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
|-
| 02DD
| 02DD
| [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]]
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|PICA_REG_VS_PROG_SWIZZLE_DATA7
| unsigned, Culling mode
| unsigned, Culling mode
|}
|}
This register is used to configure the face culling mode.
Culling mode values:
Culling mode values:
| float1.7.16, width / 2
| float1.7.16, width / 2
|}
|}
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.
=== GPUREG_VIEWPORT_INVW ===
=== GPUREG_VIEWPORT_INVW ===
| float1.7.23, 2 / width
| float1.7.23, 2 / width
|}
|}
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.
=== GPUREG_VIEWPORT_HEIGHT ===
=== GPUREG_VIEWPORT_HEIGHT ===
| float1.7.16, height / 2
| float1.7.16, height / 2
|}
|}
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.
=== GPUREG_VIEWPORT_INVH ===
=== GPUREG_VIEWPORT_INVH ===
| float1.7.23, 2 / height
| float1.7.23, 2 / height
|}
|}
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.
=== GPUREG_FRAGOP_CLIP ===
=== GPUREG_FRAGOP_CLIP ===
| unsigned, Enabled (0 = disabled, 1 = enabled)
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}
|}
This register is used to enable clipping planes.
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===
|-
|-
| 0-23
| 0-23
| float1.7.16, Clipping plane coefficient
| float1.7.16, Clipping plane coefficient ''i''
|}
|}
This register is used to configure clipping plane coefficients.
=== GPUREG_DEPTHMAP_SCALE ===
=== GPUREG_DEPTHMAP_SCALE ===
| float1.7.16, Near - Far
| float1.7.16, Near - Far
|}
|}
This register is used to configure the depth range scale.
=== GPUREG_DEPTHMAP_OFFSET ===
=== GPUREG_DEPTHMAP_OFFSET ===
|-
|-
| 0-23
| 0-23
| float1.7.16, Near
| float1.7.16, Near + Polygon Offset
|}
|}
This register is used to configure the depth range bias.
=== GPUREG_SH_OUTMAP_TOTAL ===
=== GPUREG_SH_OUTMAP_TOTAL ===
| unsigned, Number of following attributes
| unsigned, Number of following attributes
|}
|}
This register is used to configure the total shader output map attributes.
=== GPUREG_SH_OUTMAP_O''i'' ===
=== GPUREG_SH_OUTMAP_O''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
Semantic values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
| unsigned, Early depth function
| unsigned, Early depth function
|}
|}
This register configures the early depth test function.
Early depth function values:
Early depth function values:
| unsigned, Enabled (0 = disabled, 1 = enabled)
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}
|}
This register sets whether the early depth test is enabled.
=== GPUREG_EARLYDEPTH_CLEAR ===
=== GPUREG_EARLYDEPTH_CLEAR ===
| unsigned, Trigger (0 = idle, 1 = clear)
| unsigned, Trigger (0 = idle, 1 = clear)
|}
|}
This register triggers clearing the early depth data.
=== GPUREG_SH_OUTATTR_MODE ===
=== GPUREG_SH_OUTATTR_MODE ===
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}
|}
This register is used to configure the shader output attribute mode.
=== GPUREG_SCISSORTEST_MODE ===
=== GPUREG_SCISSORTEST_MODE ===
| unsigned, Enabled (0 = disabled, 3 = enabled)
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}
|}
This register is used to enable scissor testing.
=== GPUREG_SCISSORTEST_POS ===
=== GPUREG_SCISSORTEST_POS ===
| unsigned, Y1
| unsigned, Y1
|}
|}
This register is used to configure the scissor test start position.
=== GPUREG_SCISSORTEST_DIM ===
=== GPUREG_SCISSORTEST_DIM ===
| unsigned, Y2
| unsigned, Y2
|}
|}
This register is used to configure the scissor test end position.
=== GPUREG_VIEWPORT_XY ===
=== GPUREG_VIEWPORT_XY ===
|-
|-
| 0-9
| 0-9
| unsigned, X
| signed, X
|-
|-
| 16-25
| 16-25
| unsigned, Y
| signed, Y
|}
|}
This register is used to configure the viewport position.
=== GPUREG_EARLYDEPTH_DATA ===
=== GPUREG_EARLYDEPTH_DATA ===
| unsigned, Clear value
| unsigned, Clear value
|}
|}
This register is used to configure the early depth clear value.
=== GPUREG_DEPTHMAP_ENABLE ===
=== GPUREG_DEPTHMAP_ENABLE ===
| unsigned, Enabled (0 = disabled, 1 = enabled)
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}
|}
This register is used to enable depth range.
=== GPUREG_RENDERBUF_DIM ===
=== GPUREG_RENDERBUF_DIM ===
| 0x1
| 0x1
|}
|}
This register is used to configure the output framebuffer dimensions.
=== GPUREG_SH_OUTATTR_CLOCK ===
=== GPUREG_SH_OUTATTR_CLOCK ===
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}
|}
This register controls the clock supply to parts relating to certain attributes.
== Texturing registers ==
== Texturing registers ==
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
|-
| 17
| 17-31
| 0x0
| 0x0
|}
|}
This register is used to enable texture units.
Texture 3 coordinates values:
Texture 3 coordinates values:
| unsigned, Alpha
| unsigned, Alpha
|}
|}
This register is used to set a texture unit's border color.
=== GPUREG_TEXUNIT''i''_DIM ===
=== GPUREG_TEXUNIT''i''_DIM ===
| unsigned, Width
| unsigned, Width
|}
|}
This register is used to set a texture unit's dimensions.
=== GPUREG_TEXUNIT''i''_PARAM ===
=== GPUREG_TEXUNIT''i''_PARAM ===
|-
|-
| 4-5
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
|-
| 8-10
| 8-10
| unsigned, Wrap S
| unsigned, Wrap S
|-
|-
| 16
| 16-17
| 0x0
| 0x0
|-
|-
| unsigned, Type (Texture 0 only)
| unsigned, Type (Texture 0 only)
|}
|}
This register is used to set a texture unit's extra parameters.
Filter values:
Filter values:
| unsigned, Min Level
| unsigned, Min Level
|}
|}
This register is used to configure a texture unit's level of detail.
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}
|}
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.
If the texture is a cube:
If the texture is a cube:
|-
|-
| 0
| 0
| unsigned, Perspective (0 = not perspective, 1 = perspective)
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
|-
| 1-23
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
| fixed0.0.24, Z bias (upper 23 bits)
|}
|}
This register is used to set a texture unit's shadow texture properties.
=== GPUREG_TEXUNIT''i''_TYPE ===
=== GPUREG_TEXUNIT''i''_TYPE ===
|-
|-
| 0-3
| 0-3
| unsigned, [[GPU_Textures#Texture_color_types|Format]]
| unsigned, Format
|}
|}
This register is used to set a texture unit's data format.
Format values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
! GL Format
! GL Data Type
|-
|-
| 0-2
| 0x0
| unsigned, U-direction clamp
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
|-
| 3-5
| 0x1
| unsigned, V-direction clamp
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
|-
| 6-9
| 0x2
| unsigned, RGB mapping function
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}
=== GPUREG_LIGHTING_ENABLE0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}
This register is used to enable lighting.
=== GPUREG_TEXUNIT3_PROCTEX0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
|-
| 10-13
| 10-13
| float1.5.10, Texture bias (lower 8 bits)
| float1.5.10, Texture bias (lower 8 bits)
|}
|}
This register is used to configure the procedural texture unit.
Clamp values:
Clamp values:
|-
|-
| 1
| 1
| U2
| U²
|-
|-
| 2
| 2
|-
|-
| 3
| 3
| V2
| V²
|-
|-
| 4
| 4
| U + V
| (U + V) / 2
|-
|-
| 5
| 5
| U2 + V2
| (U² + V²) / 2
|-
|-
| 6
| 6
| sqrt(U2 + V2)
| sqrt(U² + V²)
|-
|-
| 7
| 7
| float1.5.10, U-direction noise phase
| float1.5.10, U-direction noise phase
|}
|}
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.
=== GPUREG_TEXUNIT3_PROCTEX2 ===
=== GPUREG_TEXUNIT3_PROCTEX2 ===
| float1.5.10, V-direction noise phase
| float1.5.10, V-direction noise phase
|}
|}
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.
=== GPUREG_TEXUNIT3_PROCTEX3 ===
=== GPUREG_TEXUNIT3_PROCTEX3 ===
| float1.5.10, V-direction noise frequency
| float1.5.10, V-direction noise frequency
|}
|}
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.
=== GPUREG_TEXUNIT3_PROCTEX4 ===
=== GPUREG_TEXUNIT3_PROCTEX4 ===
| unsigned, Minification filter
| unsigned, Minification filter
|-
|-
| 3-10
| 3-6
| 0x60
| Min LOD (usually 0)
|-
| 7-10
| Max LOD (usually 6)
|-
|-
| 11-18
| 11-18
| float1.5.10, Texture bias (upper 8 bits)
| float1.5.10, Texture bias (upper 8 bits)
|}
|}
This register is used to configure the procedural texture unit.
Minification filter values:
Minification filter values:
|-
|-
| 0-7
| 0-7
| unsigned, Texture offset
| unsigned, Texture offset (Mipmap level 0 / base level)
|-
| 8-15
| unsigned, mipmap level 1 offset (usually 0x80)
|-
|-
| 8-31
| 16-23
| 0xE0C080
| unsigned, mipmap level 2 offset (usually 0xC0)
|-
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
|}
|}
This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .
=== GPUREG_PROCTEX_LUT ===
=== GPUREG_PROCTEX_LUT ===
| unsigned, Reference table
| unsigned, Reference table
|}
|}
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.
Reference table values:
Reference table values:
|-
|-
| 12-23
| 12-23
| fixed1.0.11, Difference from next element
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
|}
|}
|-
|-
| 12-23
| 12-23
| fixed1.0.11, Difference from next element
| fixed0.0.12 with two's complement, Difference from next element
|}
|}
|-
|-
| 12-23
| 12-23
| fixed1.0.11, Difference from next element
| fixed0.0.12 with two's complement, Difference from next element
|}
|}
|-
|-
| 0-7
| 0-7
| fixed1.0.7, Red difference between current and next color table elements
| signed, Half of red difference between current and next color table elements
|-
|-
| 8-15
| 8-15
| fixed1.0.7, Green difference between current and next color table elements
| signed, Half of green difference between current and next color table elements
|-
|-
| 16-23
| 16-23
| fixed1.0.7, Blue difference between current and next color table elements
| signed, Half of blue difference between current and next color table elements
|-
|-
| 24-31
| 24-31
| fixed1.0.7, Alpha difference between current and next color table elements
| signed, Half of alpha difference between current and next color table elements
|}
|}
| unsigned, Alpha source 2
| unsigned, Alpha source 2
|}
|}
This register configures a texture combiner's sources.
Source values:
Source values:
| unsigned, Alpha operand 2
| unsigned, Alpha operand 2
|}
|}
This register configures a texture combiner's operands.
RGB operand values:
RGB operand values:
| unsigned, Alpha combine
| unsigned, Alpha combine
|}
|}
This register configures a texture combiner's combine mode.
Combine values:
Combine values:
| unsigned, Alpha
| unsigned, Alpha
|}
|}
This register configures a texture combiner's constant color.
=== GPUREG_TEXENV''i''_SCALE ===
=== GPUREG_TEXENV''i''_SCALE ===
| unsigned, Alpha scale
| unsigned, Alpha scale
|}
|}
This register configures a texture combiner's scale value.
Scale values:
Scale values:
|}
|}
This register is shared between the gas/fog mode configuration and TexEnv buffer inputs. TexEnv buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.
Fog mode values:
Fog mode values:
| unsigned, Blue
| unsigned, Blue
|}
|}
This register is used to configure the color of fog.
=== GPUREG_GAS_ATTENUATION ===
=== GPUREG_GAS_ATTENUATION ===
| float1.5.10, Gas density attenuation
| float1.5.10, Gas density attenuation
|}
|}
This register is used to configure the gas density attenuation.
=== GPUREG_GAS_ACCMAX ===
=== GPUREG_GAS_ACCMAX ===
| float1.5.10, Gas maximum density accumulation
| float1.5.10, Gas maximum density accumulation
|}
|}
This register is used to configure the gas maximum density accumulation.
=== GPUREG_FOG_LUT_INDEX ===
=== GPUREG_FOG_LUT_INDEX ===
| unsigned, Index
| unsigned, Index
|}
|}
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.
=== GPUREG_FOG_LUT_DATA''i'' ===
=== GPUREG_FOG_LUT_DATA''i'' ===
| unsigned, Alpha
| unsigned, Alpha
|}
|}
This register is used to configure the texture combiner buffer color.
== Framebuffer registers ==
== Framebuffer registers ==
| 0x0E4
| 0x0E4
|}
|}
This register is used to configure the fragment operation mode and whether to use logic ops or blending.
Fragment operation mode values:
Fragment operation mode values:
|}
|}
Equation values:
This register is used to configure the blending function.
'''Equation values:'''
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
Function values:
Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)
'''Function values:'''
{| class="wikitable" border="1"
{| class="wikitable" border="1"
| unsigned, Logic op
| unsigned, Logic op
|}
|}
This register is used to configure the logic op.
Logic op values:
Logic op values:
| unsigned, Alpha
| unsigned, Alpha
|}
|}
This register is used to configure the blending color.
=== GPUREG_FRAGOP_ALPHA_TEST ===
=== GPUREG_FRAGOP_ALPHA_TEST ===
| unsigned, Reference value
| unsigned, Reference value
|}
|}
This register is used to configure alpha testing.
Function values:
Function values:
| unsigned, Mask
| unsigned, Mask
|}
|}
This register is used to configure stencil testing.
Function values:
Function values:
| unsigned, Z-pass operation
| unsigned, Z-pass operation
|}
|}
This register is used to configure stencil result operations.
Operation values:
Operation values:
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}
|}
This register is used to depth testing and framebuffer write masking.
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.
Depth function values:
Depth function values:
| unsigned, Allow read (0 = disable, 0xF = enable)
| unsigned, Allow read (0 = disable, 0xF = enable)
|}
|}
This register configures read access from the color buffer.
=== GPUREG_COLORBUFFER_WRITE ===
=== GPUREG_COLORBUFFER_WRITE ===
| unsigned, Allow write (0 = disable, 0xF = enable)
| unsigned, Allow write (0 = disable, 0xF = enable)
|}
|}
This register configures write access to the color buffer.
=== GPUREG_DEPTHBUFFER_READ ===
=== GPUREG_DEPTHBUFFER_READ ===
| unsigned, Allow depth read (0 = disable, 1 = enable)
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}
|}
This register configures read access from the depth and stencil buffers.
=== GPUREG_DEPTHBUFFER_WRITE ===
=== GPUREG_DEPTHBUFFER_WRITE ===
| unsigned, Allow depth write (0 = disable, 1 = enable)
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}
|}
This register configures write access to the depth and stencil buffers.
=== GPUREG_DEPTHBUFFER_FORMAT ===
=== GPUREG_DEPTHBUFFER_FORMAT ===
| unsigned, Format
| unsigned, Format
|}
|}
This register configures the depth buffer data format.
Format values:
Format values:
| unsigned, Format
| unsigned, Format
|}
|}
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.
Pixel size values:
Pixel size values:
| RGBA4
| RGBA4
|}
|}
=== GPUREG_EARLYDEPTH_TEST2 ===
=== GPUREG_EARLYDEPTH_TEST2 ===
| unsigned, Enabled (0 = disabled, 1 = enabled)
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}
|}
This register enables the early depth test.
=== GPUREG_FRAMEBUFFER_BLOCK32 ===
=== GPUREG_FRAMEBUFFER_BLOCK32 ===
|}
|}
To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.
Render block mode values:
Render block mode values:
| unsigned, Depth buffer physical address >> 3
| unsigned, Depth buffer physical address >> 3
|}
|}
This register configures the depth buffer physical address.
=== GPUREG_COLORBUFFER_LOC ===
=== GPUREG_COLORBUFFER_LOC ===
| unsigned, Color buffer physical address >> 3
| unsigned, Color buffer physical address >> 3
|}
|}
This register configures the color buffer physical address.
=== GPUREG_FRAMEBUFFER_DIM ===
=== GPUREG_FRAMEBUFFER_DIM ===
| 0x1
| 0x1
|}
|}
This register configures the framebuffer dimensions.
=== GPUREG_GAS_LIGHT_XY ===
=== GPUREG_GAS_LIGHT_XY ===
| unsigned, Planar shading density attenuation
| unsigned, Planar shading density attenuation
|}
|}
This register configures gas light planar shading.
=== GPUREG_GAS_LIGHT_Z ===
=== GPUREG_GAS_LIGHT_Z ===
| unsigned, View shading density attenuation
| unsigned, View shading density attenuation
|}
|}
This register configures gas light view shading.
=== GPUREG_GAS_LIGHT_Z_COLOR ===
=== GPUREG_GAS_LIGHT_Z_COLOR ===
| 0-7
| 0-7
| unsigned, View shading effect in line-of-sight direction
| unsigned, View shading effect in line-of-sight direction
|-
| 8
| Gas color LUT input
|}
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.
Color LUT input values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Gas density
|-
| 1
| Light factor
|}
|}
| unsigned, Index
| unsigned, Index
|}
|}
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.
=== GPUREG_GAS_LUT_DATA ===
=== GPUREG_GAS_LUT_DATA ===
|}
|}
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAAS_LUT_INDEX.
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.
==== Gas Look-Up Table ====
==== Gas Look-Up Table ====
| 0-23
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
| fixed0.16.8, Depth direction attenuation proportion
|}
|-
| 24-25
| unsigned, Depth function
|}
This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.
Gas depth function values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Greater than/Greater than or equal
|-
| 3
| Less than/Less than or equal/Equal/Not equal
|}
=== GPUREG_FRAGOP_SHADOW ===
=== GPUREG_FRAGOP_SHADOW ===
| float1.5.10, Penumbra scale with reversed sign
| float1.5.10, Penumbra scale with reversed sign
|}
|}
This register is used to configure shadow properties.
== Fragment lighting registers ==
== Fragment lighting registers ==
=== GPUREG_LIGHTING_ENABLE0 ===
=== GPUREG_LIGHT''i''_SPECULAR0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.
=== GPUREG_LIGHT''i''_SPECULAR1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| 0-7
| unsigned, Shadow factor enable, usually set to bit16 OR bit18 OR bit19
| unsigned, Blue
|-
|-
| 1
| 10-17
| Unknown, set to 0
| unsigned, Green
|-
|-
| 2-3
| 20-27
| unsigned, "Fresnel selector" (see below)
| unsigned, Red
|}
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.
=== GPUREG_LIGHT''i''_DIFFUSE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 4-7
| 0-7
| unsigned, "Config", "Light env config" (see below)
| unsigned, Blue
|-
|-
| 8-15
| 10-17
| Unknown, set to 4
| unsigned, Green
|-
|-
| 20-27
| unsigned, Red
| 20-21
| unsigned, "Clamp highlights", 0=disabled, 1=enabled
|}
|}
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.
=== GPUREG_LIGHT''i''_AMBIENT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value
! Bits
! Description
! Description
|-
|-
| 0
| 0-7
| NO_FRESNEL
| unsigned, Blue
|-
|-
| 1
| 10-17
| PRI_ALPHA_FRESNEL
| unsigned, Green
|-
|-
| 2
| 20-27
| unsigned, Red
| 3
|}
|}
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.
=== GPUREG_LIGHT''i''_XY ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value
! Bits
! Description
! Description
|-
|-
| 0
| 0-15
| LIGHT_ENV_LAYER_CONFIG0
| float1.5.10, X coordinate
|-
|-
| 1
| 16-31
| LIGHT_ENV_LAYER_CONFIG1
| float1.5.10, Y coordinate
| lut_FR, lut_RR, lut_SP, lut_DA
|}
| 2
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.
=== GPUREG_LIGHT''i''_Z ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 3
| 0-15
| LIGHT_ENV_LAYER_CONFIG3
| float1.5.10, Z coordinate
| lut_D0, lut_D1, lut_FR, lut_DA
|}
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 4
| 0-12
| LIGHT_ENV_LAYER_CONFIG4
| fixed1.1.11, X coordinate (negated)
|-
|-
| 5
| 16-28
| fixed1.1.11, Y coordinate (negated)
| 6
|}
|}
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value
! Bits
! Description
! Description
|-
|-
| 0
| 0-12
| fixed1.1.11, Z coordinate (negated)
| 1
|}
|}
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.
=== GPUREG_LIGHTING_CONFIG1 ===
=== GPUREG_LIGHT''i''_CONFIG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| unsigned, Disable bit for frag light source 0 shadows
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
|-
| 1
| 1
| unsigned, Disable bit for frag light source 1 shadows
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
|-
| 2
| 2
| unsigned, Disable bit for frag light source 2 shadows
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
|-
| 3
| 3
| unsigned, Disable bit for frag light source 3 shadows
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}
This register configures a light's properties.
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 4
| 0-19
| unsigned, Disable bit for frag light source 4 shadows
| float1.7.12, Distance attenuation bias
|}
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 5
| 0-19
| unsigned, Disable bit for frag light source 5 shadows
| float1.7.12, Distance attenuation scale
|}
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).
=== GPUREG_LIGHTING_AMBIENT ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 6
| 0-7
| unsigned, Disable bit for frag light source 6 shadows
| unsigned, Blue
|-
|-
| 7
| 10-17
| unsigned, Disable bit for frag light source 7 shadows
| unsigned, Green
|-
|-
| 8
| 20-27
| unsigned, Disable bit for frag light source 0 spot
| unsigned, Red
|}
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.
=== GPUREG_LIGHTING_NUM_LIGHTS ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 9
| 0-2
| unsigned, Disable bit for frag light source 1 spot
| unsigned, Number of active lights - 1
|}
This register configures the number of active lights.
=== GPUREG_LIGHTING_CONFIG0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 10
| 0
| unsigned, Disable bit for frag light source 2 spot
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
|-
| 11
| 2-3
| unsigned, Disable bit for frag light source 3 spot
| unsigned, Fresnel selector
|-
|-
| 12
| 4-7
| unsigned, Disable bit for frag light source 4 spot
| unsigned, Light environment configuration
|-
|-
| 13
| 8-11
| 0x4
| 14
|-
|-
| 16
| 16
| unsigned, Disable bit for lut_D0
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
|-
| 17
| 17
| unsigned, Disable bit for lut_D1
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
|-
| 18
| 18
| Unknown, set to 1
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
|-
| 19
| 19
| unsigned, Disable bit for lut_FR
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
|-
| 20
| 22-23
| unsigned, Disable bit for lut_RB
| unsigned, Bump map texture unit
|-
|-
| 21
| 24-25
| unsigned, Disable bit for lut_RG
| unsigned, Shadow map texture unit
|-
|-
| 22
| 27
| unsigned, Disable bit for lut_RR
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
|-
| 23
| 28-29
| Unknown, set to 1
| unsigned, Bump mode
|-
|-
| 24
| 30
| unsigned, Disable bit for frag light source 0 distance attenuation
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
|-
| 25
| 31
| unsigned, Disable bit for frag light source 1 distance attenuation
| 0x1
|}
This register configures the light environment.
Fresnel selector values:
{| class="wikitable" border="1"
! Value
! Description
|-
|-
| 26
| 0
| unsigned, Disable bit for frag light source 2 distance attenuation
| None
|-
|-
| 27
| 1
| unsigned, Disable bit for frag light source 3 distance attenuation
| Primary alpha
|-
|-
| 28
| 2
| unsigned, Disable bit for frag light source 4 distance attenuation
| Secondary alpha
|-
|-
| 29
| 3
| unsigned, Disable bit for frag light source 5 distance attenuation
| Primary and secondary alpha
|}
|}
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.
The number of active lights minus one (0..7) is written to this register.
Light environment configuration values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
! Available LUTs
|-
|-
| 0-2
| 0
| unsigned, ID of the 1st enabled light (0..7)
| Configuration 0
| D0, RR, SP, DA
|-
|-
| 4-6
| 1
| unsigned, ID of the 2nd enabled light (0..7)
| Configuration 1
| FR, RR, SP, DA
|-
|-
| 8-10
| 2
| unsigned, ID of the 3rd enabled light (0..7)
| Configuration 2
| D0, D1, RR, DA
|-
|-
| 12-14
| 3
| unsigned, ID of the 4th enabled light (0..7)
| Configuration 3
| D0, D1, FR, DA
|-
|-
| 16-18
| 4
| unsigned, ID of the 5th enabled light (0..7)
| Configuration 4
| All except for FR
|-
|-
| 20-22
| 5
| unsigned, ID of the 6th enabled light (0..7)
| Configuration 5
| All except for D1
|-
|-
| 24-26
| 6
| unsigned, ID of the 7th enabled light (0..7)
| Configuration 6
| All except for RB and RG
|-
|-
| 28-30
| 8
| unsigned, ID of the 8th enabled light (0..7)
| Configuration 7
| All
|}
|}
Bump mode values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-3
| 0
| unsigned, Input selector for lut_D0
| Not used
|-
|-
| 4-7
| 1
| unsigned, Input selector for lut_D1
| Use as bump map
|-
|-
| 8-11
| 2
| unsigned, Input selector for lut_SP
| Use as tangent map
|}
|}
=== GPUREG_LIGHTING_CONFIG1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value
! Bits
! Description
! Description
|-
|-
| 0
| 0
| N·H
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 1
| 1
| V·H
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 2
| 2
| N·V
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 3
| 3
| L·N
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 4
| 4
| -L·P (aka Spotlight aka SP)
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 5
| 5
| cos φ (aka CP)
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|}
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 1
| 7
| unsigned, abs() flag for the input of lut_D0 (0=enabled, 1=disabled)
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
|-
| 5
| 8
| unsigned, abs() flag for the input of lut_D1 (0=enabled, 1=disabled)
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
|-
| 9
| 9
| unsigned, abs() flag for the input of lut_SP (0=enabled, 1=disabled)
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
|-
| 13
| 13
| unsigned, abs() flag for the input of lut_FR (0=enabled, 1=disabled)
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
|-
| 17
| 17
| unsigned, abs() flag for the input of lut_RB (0=enabled, 1=disabled)
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20-22
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|-
|-
| 21
| 21
| unsigned, abs() flag for the input of lut_RG (0=enabled, 1=disabled)
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
|-
| 25
| 25
| unsigned, abs() flag for the input of lut_RR (0=enabled, 1=disabled)
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}
|}
This register controls whether the absolute value of the input is taken before using a LUT.
This register is used to disable various aspects of the light environment.
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===
=== GPUREG_LIGHTING_LUT_INDEX ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-3
| 0-7
| unsigned, Scaler selector for lut_D0
| unsigned, Starting index
|-
|-
| 8-12
| unsigned, Look-up table
| 8-11
| unsigned, Scaler selector for lut_FR
|}
|}
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.
Lookup table values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| 1x
| D0
|-
|-
| 1
| 1
| 2x
| D1
|-
| 3
| FR
|-
|-
| 2
| 4
| 4x
| RB
|-
|-
| 3
| 5
| 8x
| RG
|-
|-
| 6
| 6
| 0.25x
| RR
|-
| 8-15
| SP0-7
|-
|-
| 7
| 16-23
| 0.5x
| DA0-7
|}
|}
=== GPUREG_LIGHTING_ENABLE1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
! Description
! Description
|-
|-
| 0-7
| 0
| unsigned, Starting entry offset (0...255)
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}
|}
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.
=== GPUREG_LIGHTING_LUT_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value
! Bits
! Description
! Description
|-
|-
| 0
| 0-23
| LUT data
|-
|}
|}
Lighting LUT data is written here.
Lighting LUT data is written here.
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.
Format of an entry:
Format of an entry:
|-
|-
| 0-11
| 0-11
| fixed0.0.12, Entry value (12bit fractional number; floatval = x / 4096; however 0xFFF is treated as 1.0)
| fixed0.0.12, Entry value
|-
|-
| 12-23
| 12-23
|}
|}
=== GPUREG_LIGHTING_AMBIENT ===
=== GPUREG_LIGHTING_LUTINPUT_ABS ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 1
| unsigned, Blue component (0..255)
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
|-
| 10-17
| 21
| unsigned, Green component (0..255)
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
|-
| 20-27
| 25
| unsigned, Red component (0..255)
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}
|}
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.
This register controls whether the absolute value of the input is taken before using a LUT.
=== GPUREG_LIGHTx_CONFIG ===
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| 0-2
| unsigned, Light type (0 = positional light, 1 = directional light)
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
|-
| 1
| 8-10
| unsigned, Two side diffuse (0=disable, 1=enable)
| unsigned, Input selector for SP
|-
|-
| 2
| 12-14
| unsigned, Geometric factor 0 (0=disable, 1=enable)
| unsigned, Input selector for FR
|-
|-
| 3
| 16-18
| unsigned, Geometric factor 1 (0=disable, 1=enable)
| unsigned, Input selector for RB
|-
|-
| 0-15
| 20-22
| float1.5.10, X coordinate
| unsigned, Input selector for RG
|-
|-
| 16-31
| 24-26
| float1.5.10, Y coordinate
| unsigned, Input selector for RR
|}
|}
This register selects the input from LUTs.
Input selector values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-15
| 0
| float1.5.10, Z coordinate
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}
|}
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===
=== GPUREG_LIGHTx_SPOTDIR_XY ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-12
| 0-2
| fixed1.1.11, X coordinate (Usually the input value is negated)
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
|-
| 16-28
| 8-10
| fixed1.1.11, Y coordinate (Usually the input value is negated)
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}
|}
This register controls the scaling that is applied to the output of a LUT.
Scaler selector values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-12
| 0
| fixed1.1.11, Z coordinate (Usually the input value is negated)
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}
|}
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===
=== GPUREG_LIGHTx_ATTENUATION_BIAS ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-2
| unsigned, Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
| unsigned, ID of the 1st enabled light
|-
|-
| 8
| 4-6
| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''
| unsigned, ID of the 2nd enabled light
|-
|-
| 9-15
| 8-10
| No effect.
| unsigned, ID of the 3rd enabled light
|-
|-
| 16-23
| 12-14
| Unknown.
| unsigned, ID of the 4th enabled light
|-
|-
| 24-31
| 16-18
| Unknown. Often set to 0.
| unsigned, ID of the 5th enabled light
|}
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
|-
| 0-31
| 28-30
| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline.
| unsigned, ID of the 8th enabled light
|}
|}
This register sets the IDs of enabled light sources.
== Geometry pipeline registers ==
=== GPUREG_ATTRIBBUFFERS_LOC ===
=== GPUREG_RESTART_PRIMITIVE ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 1-28
| Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]], but most games seem to write to it before every draw call.
| unsigned, Vertex arrays base address
|}
|}
This register sets the base address of all vertex arrays.
=== GPUREG_GSH_BOOLUNIFORM ===
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| 0-1
| unsigned, Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 0 type
|-
|-
| 1
| 2-3
| unsigned, Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 0 size
|-
|-
| 2
| 4-5
| unsigned, Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 1 type
|-
|-
| 3
| 6-7
| unsigned, Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 1 size
|-
|-
| 4
| 8-9
| unsigned, Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 2 type
|-
|-
| 5
| 10-11
| unsigned, Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 2 size
|-
|-
| 6
| 12-13
| unsigned, Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 3 type
|-
|-
| 7
| 14-15
| unsigned, Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 3 size
|-
|-
| 8
| 16-17
| unsigned, Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 4 type
|-
|-
| 9
| 18-19
| unsigned, Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 4 size
|-
|-
| 10
| 20-21
| unsigned, Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 5 type
|-
|-
| 11
| 22-23
| unsigned, Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 5 size
|-
|-
| 12
| 24-25
| unsigned, Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 6 type
|-
|-
| 13
| 26-27
| unsigned, Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 6 size
|-
|-
| 14
| 28-29
| unsigned, Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
| unsigned, Vertex attribute 7 type
|-
|-
| 15
| 30-31
| unsigned, Vertex attribute 7 size
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
|}
|}
This register is used to set the geometry shader unit's boolean registers.
This register configures the types and sizes of the first 8 vertex attributes.
Vertex attribute type values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-7
| 0
| unsigned, Value for geometry shader's i0.x
| Byte
|-
|-
| 8-15
| 1
| unsigned, Value for geometry shader's i0.y
| Unsigned byte
|-
|-
| 16-23
| 2
| unsigned, Value for geometry shader's i0.z
| Short
|-
|-
| 24-31
| 3
| unsigned, Value for geometry shader's i0.w
| Float
|}
|}
Vertex attribute size values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-7
| 0
| unsigned, Value for geometry shader's i1.x
| 8 bits
|-
|-
| 8-15
| 1
| unsigned, Value for geometry shader's i1.y
| 16 bits
|-
|-
| 16-23
| 2
| unsigned, Value for geometry shader's i1.z
| 24 bits
|-
|-
| 24-31
| 3
| unsigned, Value for geometry shader's i1.w
| 32 bits
|}
|}
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===
=== GPUREG_GSH_INTUNIFORM_I2 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-1
| unsigned, Value for geometry shader's i2.x
| unsigned, Vertex attribute 8 type
|-
|-
| 8-15
| 2-3
| unsigned, Value for geometry shader's i2.y
| unsigned, Vertex attribute 8 size
|-
|-
| 16-23
| 4-5
| unsigned, Value for geometry shader's i2.z
| unsigned, Vertex attribute 9 type
|-
|-
| 0-7
| 6-7
| unsigned, Value for geometry shader's i3.x
| unsigned, Vertex attribute 9 size
|-
|-
| 8-15
| 8-9
| unsigned, Value for geometry shader's i3.y
| unsigned, Vertex attribute 10 type
|-
|-
| 16-23
| 10-11
| unsigned, Value for geometry shader's i3.z
| unsigned, Vertex attribute 10 size
|-
|-
| 24-31
| 12-13
| unsigned, Value for geometry shader's i3.w
| unsigned, Vertex attribute 11 type
|-
|-
| 0-7
| 14-15
| unsigned, Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
| unsigned, Vertex attribute 11 size
|-
|-
| 8-23
| 16-27
| Unknown. These bits typically aren't updated by games.
| unsigned, Fixed vertex attribute mask
|-
|-
| 24-31
| 28-31
| Unknown. This is typically set to 8 for geometry shaders.
| unsigned, Total vertex attribute count - 1
|}
|}
This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.
=== GPUREG_GSH_ENTRYPOINT ===
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-15
| 0-27
| unsigned, Geometry shader unit entrypoint, in words.
| unsigned, Offset from base vertex arrays address
|}
|}
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
This register configures the offset of a vertex array from the base vertex arrays address.
=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-3
| 0-3
| unsigned, Index of geometry shader input register which the 1st attribute will be stored in.
| unsigned, Component 1
|-
|-
| 4-7
| 4-7
| unsigned, Index of geometry shader input register which the 2nd attribute will be stored in.
| unsigned, Component 2
|-
|-
| 8-11
| 8-11
| unsigned, Index of geometry shader input register which the 3rd attribute will be stored in.
| unsigned, Component 3
|-
|-
| 12-15
| 12-15
| unsigned, Index of geometry shader input register which the 4th attribute will be stored in.
| unsigned, Component 4
|-
|-
| 16-19
| 16-19
| unsigned, Index of geometry shader input register which the 5th attribute will be stored in.
| unsigned, Component 5
|-
|-
| 20-23
| 20-23
| unsigned, Index of geometry shader input register which the 6th attribute will be stored in.
| unsigned, Component 6
|-
|-
| 24-27
| 24-27
| unsigned, Index of geometry shader input register which the 7th attribute will be stored in.
| unsigned, Component 7
|-
|-
| 28-31
| 28-31
| unsigned, Index of geometry shader input register which the 8th attribute will be stored in.
| unsigned, Component 8
|}
|}
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
This register configures the first 8 component types of a vertex array.
Component values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-3
| 0
| unsigned, Index of geometry shader input register which the 9th attribute will be stored in.
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
|-
| 4-7
| 2
| unsigned, Index of geometry shader input register which the 10th attribute will be stored in.
| Vertex attribute 2
|-
|-
| 8-11
| 3
| unsigned, Index of geometry shader input register which the 11th attribute will be stored in.
| Vertex attribute 3
|-
|-
| 12-15
| 4
| unsigned, Index of geometry shader input register which the 12th attribute will be stored in.
| Vertex attribute 4
|-
|-
| 16-19
| 5
| unsigned, Index of geometry shader input register which the 13th attribute will be stored in.
| Vertex attribute 5
|-
|-
| 20-23
| 6
| unsigned, Index of geometry shader input register which the 14th attribute will be stored in.
| Vertex attribute 6
|-
|-
| 24-27
| 7
| unsigned, Index of geometry shader input register which the 15th attribute will be stored in.
| Vertex attribute 7
|-
|-
| 28-31
| 8
| Vertex attribute 8
|}
|-
|-
| 0
| 9
| unsigned, Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
| Vertex attribute 9
|-
|-
| 1
| 10
| unsigned, Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
| Vertex attribute 10
|-
|-
| 2
| 11
| unsigned, Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
| Vertex attribute 11
|-
|-
| 3
| 12
| unsigned, Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
| 4-byte padding
|-
|-
| 4
| 13
| unsigned, Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
| 8-byte padding
|-
|-
| 5
| 14
| unsigned, Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
| 12-byte padding
|-
|-
| 6
| 15
| unsigned, Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
| 16-byte padding
|}
|}
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===
=== GPUREG_GSH_CODETRANSFER_END ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| 0-3
| unsigned, Code data transfer end signal bit.
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}
|}
This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.
=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.
=== GPUREG_INDEXBUFFER_CONFIG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-6
| 0-27
| unsigned, Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
| unsigned, Offset from base vertex arrays address
|-
|-
| 31
| 31
| unsigned, Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}
|}
This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
This register configures the index array used when drawing elements.
=== GPUREG_GSH_FLOATUNIFORM_DATA ===
=== GPUREG_NUMVERTICES ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
| unsigned, Number of vertices to render
|}
|}
This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].
This register sets the number of vertices to render.
=== GPUREG_GEOSTAGE_CONFIG ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}
This register configures the geometry stage of the GPU pipeline.
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.
=== GPUREG_GSH_CODETRANSFER_CONFIG ===
=== GPUREG_VERTEX_OFFSET ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-11
| 0-31
| unsigned, Target geometry shader code offset for data transfer.
| unsigned, Starting vertex offset
|}
|}
This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.
This register sets the offset of the first vertex in an array to render.
=== GPUREG_POST_VERTEX_CACHE_NUM ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}
This register configures the post-vertex cache.
=== GPUREG_GSH_CODETRANSFER_DATA ===
=== GPUREG_DRAWARRAYS ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| unsigned, Geometry shader instruction data.
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}
|}
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
This register triggers drawing vertex arrays.
=== GPUREG_GSH_OPDESCS_CONFIG ===
=== GPUREG_DRAWELEMENTS ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-6
| 0-31
| unsigned, Target geometry shader operand descriptor offset for data transfer.
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}
|}
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
This register triggers drawing vertex array elements.
=== GPUREG_GSH_OPDESCS_DATA ===
=== GPUREG_VTX_FUNC ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| unsigned, Geometry shader operand descriptor data.
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}
|}
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
This register triggers clearing the post-vertex cache.
=== GPUREG_FIXEDATTRIB_INDEX ===
== Vertex shader registers ==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}
=== GPUREG_VSH_BOOLUNIFORM ===
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.
=== GPUREG_FIXEDATTRIB_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| colspan="2" | '''DATA0:'''
| unsigned, Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
|-
|-
| 1
| 0-7
| unsigned, Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
|-
| 2
| 8-31
| unsigned, Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
| float1.7.16, Vertex attribute element 4 (W)
|-
|-
| 3
| colspan="2" | '''DATA1:'''
| unsigned, Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
|-
|-
| 4
| 0-15
| unsigned, Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
|-
| 5
| 16-31
| unsigned, Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
|-
| 6
| colspan="2" | '''DATA2:'''
| unsigned, Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
|-
|-
| 7
| 0-23
| unsigned, Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
| float1.7.16, Vertex attribute element 1 (X)
|-
|-
| 8
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
| 9
|}
|}
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
=== GPUREG_VSH_INTUNIFORM_I0 ===
=== GPUREG_CMDBUF_SIZE0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-20
| unsigned, Value for vertex shader's i0.x
| unsigned, Size of command buffer 0 >> 3
|}
|}
This register is used to set the vertex shader's i0 integer register.
This register sets the size of the first command buffer.
=== GPUREG_VSH_INTUNIFORM_I1 ===
=== GPUREG_CMDBUF_SIZE1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-20
| unsigned, Value for vertex shader's i1.x
| unsigned, Size of command buffer 1 >> 3
|}
|}
This register is used to set the vertex shader's i1 integer register.
This register sets the size of the second command buffer.
=== GPUREG_VSH_INTUNIFORM_I2 ===
=== GPUREG_CMDBUF_ADDR0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-28
| unsigned, Value for vertex shader's i2.x
| unsigned, Physical address of command buffer 0 >> 3
|}
|}
This register is used to set the vertex shader's i2 integer register.
This register sets the physical address of the first command buffer.
=== GPUREG_VSH_INTUNIFORM_I3 ===
=== GPUREG_CMDBUF_ADDR1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-28
| unsigned, Value for vertex shader's i3.x
| unsigned, Physical address of command buffer 1 >> 3
|}
|}
This register is used to set the vertex shader's i3 integer register.
This register sets the physical address of the second command buffer.
=== GPUREG_VSH_INPUTBUFFER_CONFIG ===
=== GPUREG_CMDBUF_JUMP0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-31
| unsigned, Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}
|}
This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.
This register triggers a jump to the first command buffer.
=== GPUREG_VSH_ENTRYPOINT ===
=== GPUREG_CMDBUF_JUMP1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-15
| 0-31
| unsigned, Vertex shader entrypoint, in words.
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}
|}
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
This register triggers a jump to the second command buffer.
=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===
=== GPUREG_VSH_NUM_ATTR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-3
| 0-3
| unsigned, Index of vertex shader input register which the 1st attribute will be stored in.
| unsigned, Number of vertex shader input attributes - 1
|}
This register sets the number of vertex shader input attributes.
=== GPUREG_VSH_COM_MODE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 4-7
| 0
| unsigned, Index of vertex shader input register which the 2nd attribute will be stored in.
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.
=== GPUREG_START_DRAW_FUNC0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 8-11
| 0
| unsigned, Index of vertex shader input register which the 3rd attribute will be stored in.
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
|-
| 12-15
| 1-7
| unsigned, Index of vertex shader input register which the 4th attribute will be stored in.
| 0x0
|}
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.
=== GPUREG_VSH_OUTMAP_TOTAL1 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 16-19
| 0-3
| unsigned, Index of vertex shader input register which the 5th attribute will be stored in.
| unsigned, Number of vertex shader output map registers - 1
|}
|}
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
This register sets the number of vertex shader output map registers.
=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===
=== GPUREG_VSH_OUTMAP_TOTAL2 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-3
| 0-3
| unsigned, Index of vertex shader input register which the 9th attribute will be stored in.
| unsigned, Number of vertex shader output map registers - 1
|}
|}
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
This register sets the number of vertex shader output map registers.
=== GPUREG_VSH_OUTMAP_MASK ===
=== GPUREG_GSH_MISC0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| 0-31
| unsigned, Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}
This register configures miscellaneous geometry shader properties.
=== GPUREG_GEOSTAGE_CONFIG2 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 1
| 0
| unsigned, Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
|-
| 2
| 8
| unsigned, Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}
This register configures the geometry stage of the GPU pipeline.
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.
=== GPUREG_GSH_MISC1 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 3
| 0-4
| unsigned, Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.
=== GPUREG_PRIMITIVE_CONFIG ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 4
| 0-3
| unsigned, Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
| unsigned, Number of vertex shader output map registers - 1
|-
|-
| 5
| 8-9
| unsigned, Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
| unsigned, Primitive mode
|}
This register configures primitive drawing.
Primitive mode value:
{| class="wikitable" border="1"
! Value
! Description
|-
|-
| 6
| 0
| unsigned, Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
| Triangles
|-
|-
| 7
| 1
| unsigned, Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
| Triangle strip
|-
|-
| 8
| 2
| unsigned, Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
| Triangle fan
|-
|-
| 9
| 3
| unsigned, Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
| Geometry primitive
|}
=== GPUREG_RESTART_PRIMITIVE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}
This register triggers resetting primitive drawing.
== Shader registers ==
=== GPUREG_''SH''_BOOLUNIFORM ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
|-
| 10
| 10
| unsigned, Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
|-
| 11
| 11
| unsigned, Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
|-
| 12
| 12
| unsigned, Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
|-
| 13
| 13
| unsigned, Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
|-
| 14
| 14
| unsigned, Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
|-
| 15
| 15
| unsigned, Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|}
|-
| 16-31
This register toggles the vertex shader units' output registers.
| 0x7FFF
|}
=== GPUREG_VSH_CODETRANSFER_END ===
This register is used to set a shader unit's boolean registers.
{| class="wikitable" border="1"
! Bits
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===
! Description
|-
{| class="wikitable" border="1"
| 0
! Bits
| unsigned, Code data transfer end signal bit.
! Description
|}
|-
| 0-7
This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.
| unsigned, Integer register i''i'' X value
|-
=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===
| 8-15
| unsigned, Integer register i''i'' Y value
{| class="wikitable" border="1"
|-
! Bits
| 16-23
! Description
| unsigned, Integer register i''i'' Z value
|-
|-
| 0-6
| 24-31
| unsigned, Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
| unsigned, Integer register i''i'' W value
|-
|}
| 31
| unsigned, Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
These registers are used to set a shader unit's integer registers.
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}
This register is used to configure a shader unit's input buffer.
=== GPUREG_''SH''_ENTRYPOINT ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}
This register sets a shader unit's code entry point.
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.
=== GPUREG_''SH''_OUTMAP_MASK ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}
This register toggles a shader unit's output registers.
=== GPUREG_''SH''_CODETRANSFER_END ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}
This register's value should be set to 1 in order to finalize the transfer of shader code.
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
=== GPUREG_''SH''_CODETRANSFER_INDEX ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}
|}
This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.
=== GPUREG_VSH_FLOATUNIFORM_DATA ===
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
| unsigned, Shader instruction data
|}
|}
This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.
=== GPUREG_VSH_CODETRANSFER_CONFIG ===
=== GPUREG_''SH''_OPDESCS_INDEX ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-11
| 0-11
| unsigned, Target vertex shader code offset for data transfer.
| unsigned, Target shader operand descriptor offset
|}
|}
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.
=== GPUREG_VSH_CODETRANSFER_DATA ===
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| unsigned, Vertex shader instruction data.
| unsigned, Shader operand descriptor data
|}
|}
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.