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GPU/Internal Registers (edit)

Revision as of 05:11, 18 January 2019

607 bytes added ,  05:11, 18 January 2019
→‎Command Header: Size field is 8-bit, not 11-bit (tested on hardware)
Line 26: Line 26:  
| Parameter mask
 
| Parameter mask
 
|-
 
|-
−
| 20-30
+
| 20-27
 
| Number of extra parameters (may be zero)
 
| Number of extra parameters (may be zero)
 +
|-
 +
| 28-30
 +
| Unused
 
|-
 
|-
 
| 31
 
| 31
Line 2,938: Line 2,941:  
|-
 
|-
 
| 0233
 
| 0233
−
| [[#GPUREG_FIXEDATTRIB_DATA0|GPUREG_FIXEDATTRIB_DATA0]]
+
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
 
|?
 
|?
 
|PICA_REG_VS_FIXED_ATTR_DATA0
 
|PICA_REG_VS_FIXED_ATTR_DATA0
 
|-
 
|-
 
| 0234
 
| 0234
−
| [[#GPUREG_FIXEDATTRIB_DATA1|GPUREG_FIXEDATTRIB_DATA1]]
+
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
 
|?
 
|?
 
|PICA_REG_VS_FIXED_ATTR_DATA1
 
|PICA_REG_VS_FIXED_ATTR_DATA1
 
|-
 
|-
 
| 0235
 
| 0235
−
| [[#GPUREG_FIXEDATTRIB_DATA2|GPUREG_FIXEDATTRIB_DATA2]]
+
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
 
|?
 
|?
 
|PICA_REG_VS_FIXED_ATTR_DATA2
 
|PICA_REG_VS_FIXED_ATTR_DATA2
Line 4,364: Line 4,367:  
|-
 
|-
 
| 0-9
 
| 0-9
−
| unsigned, X
+
| signed, X
 
|-
 
|-
 
| 16-25
 
| 16-25
−
| unsigned, Y
+
| signed, Y
 
|}
 
|}
   Line 4,563: Line 4,566:  
|-
 
|-
 
| 4-5
 
| 4-5
−
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
+
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
 
|-
 
|-
 
| 8-10
 
| 8-10
Line 4,717: Line 4,720:  
|-
 
|-
 
| 0
 
| 0
−
| unsigned, Perspective (0 = not perspective, 1 = perspective)
+
| unsigned, Perspective (0 = perspective, 1 = not perspective)
 
|-
 
|-
 
| 1-23
 
| 1-23
Line 4,896: Line 4,899:  
|-
 
|-
 
| 1
 
| 1
−
| U2
+
| U²
 
|-
 
|-
 
| 2
 
| 2
Line 4,902: Line 4,905:  
|-
 
|-
 
| 3
 
| 3
−
| V2
+
| V²
 
|-
 
|-
 
| 4
 
| 4
−
| U + V
+
| (U + V) / 2
 
|-
 
|-
 
| 5
 
| 5
−
| U2 + V2
+
| (U² + V²) / 2
 
|-
 
|-
 
| 6
 
| 6
−
| sqrt(U2*U2 + V2*V2)
+
| sqrt(U² + V²)
 
|-
 
|-
 
| 7
 
| 7
Line 4,993: Line 4,996:  
| unsigned, Minification filter
 
| unsigned, Minification filter
 
|-
 
|-
−
| 3-10
+
| 3-6
−
| 0x60
+
| Min LOD (usually 0)
 +
|-
 +
| 7-10
 +
| Max LOD (usually 6)
 
|-
 
|-
 
| 11-18
 
| 11-18
Line 5,037: Line 5,043:  
|-
 
|-
 
| 0-7
 
| 0-7
−
| unsigned, Texture offset
+
| unsigned, Texture offset (Mipmap level 0 / base level)
 
|-
 
|-
−
| 8-31
+
| 8-15
−
| 0xE0C080
+
| unsigned, mipmap level 1 offset (usually 0x80)
 +
|-
 +
| 16-23
 +
| unsigned, mipmap level 2 offset (usually 0xC0)
 +
|-
 +
| 24-31
 +
| unsigned, mipmap level 3 offset (usually 0xE0)
 
|}
 
|}
   −
This register is used to set the procedural texture unit's offset.
+
This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .
    
=== GPUREG_PROCTEX_LUT ===
 
=== GPUREG_PROCTEX_LUT ===
Line 5,105: Line 5,117:  
|-
 
|-
 
| 12-23
 
| 12-23
−
| fixed1.0.11, Difference from next element
+
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
 
|}
 
|}
   Line 5,119: Line 5,131:  
|-
 
|-
 
| 12-23
 
| 12-23
−
| fixed1.0.11, Difference from next element
+
| fixed0.0.12 with two's complement, Difference from next element
 
|}
 
|}
   Line 5,133: Line 5,145:  
|-
 
|-
 
| 12-23
 
| 12-23
−
| fixed1.0.11, Difference from next element
+
| fixed0.0.12 with two's complement, Difference from next element
 
|}
 
|}
   Line 5,164: Line 5,176:  
|-
 
|-
 
| 0-7
 
| 0-7
−
| fixed1.0.7, Red difference between current and next color table elements
+
| signed, Half of red difference between current and next color table elements
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| fixed1.0.7, Green difference between current and next color table elements
+
| signed, Half of green difference between current and next color table elements
 
|-
 
|-
 
| 16-23
 
| 16-23
−
| fixed1.0.7, Blue difference between current and next color table elements
+
| signed, Half of blue difference between current and next color table elements
 
|-
 
|-
 
| 24-31
 
| 24-31
−
| fixed1.0.7, Alpha difference between current and next color table elements
+
| signed, Half of alpha difference between current and next color table elements
 
|}
 
|}
   Line 5,703: Line 5,715:  
This register is used to configure the blending function.
 
This register is used to configure the blending function.
   −
Equation values:
+
'''Equation values:'''
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 5,725: Line 5,737:  
|}
 
|}
   −
Function values:
+
Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)
 +
 
 +
'''Function values:'''
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 6,047: Line 6,061:     
This register is used to depth testing and framebuffer write masking.
 
This register is used to depth testing and framebuffer write masking.
 +
 +
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.
    
Depth function values:
 
Depth function values:
Line 6,361: Line 6,377:  
| 0-7
 
| 0-7
 
| unsigned, View shading effect in line-of-sight direction
 
| unsigned, View shading effect in line-of-sight direction
 +
|-
 +
| 8
 +
| Gas color LUT input
 
|}
 
|}
   −
This register configures gas light shading in the line-of-sight direction.
+
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.
 +
 
 +
Color LUT input values:
 +
 
 +
{| class="wikitable" border="1"
 +
! Value
 +
! Description
 +
|-
 +
| 0
 +
| Gas density
 +
|-
 +
| 1
 +
| Light factor
 +
|}
    
=== GPUREG_GAS_LUT_INDEX ===
 
=== GPUREG_GAS_LUT_INDEX ===
Line 6,431: Line 6,463:  
| 0-23
 
| 0-23
 
| fixed0.16.8, Depth direction attenuation proportion
 
| fixed0.16.8, Depth direction attenuation proportion
 +
|-
 +
| 24-25
 +
| unsigned, Depth function
 
|}
 
|}
   −
This register is used to configure the gas depth direction attenuation proportion.
+
This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.
 +
 
 +
Gas depth function values:
 +
 
 +
{| class="wikitable" border="1"
 +
! Value
 +
! Description
 +
|-
 +
| 0
 +
| Never
 +
|-
 +
| 1
 +
| Always
 +
|-
 +
| 2
 +
| Greater than/Greater than or equal
 +
|-
 +
| 3
 +
| Less than/Less than or equal/Equal/Not equal
 +
|}
    
=== GPUREG_FRAGOP_SHADOW ===
 
=== GPUREG_FRAGOP_SHADOW ===
Line 7,545: Line 7,599:  
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.
 
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.
   −
=== GPUREG_FIXEDATTRIB_DATA0 ===
+
=== GPUREG_FIXEDATTRIB_DATA''i'' ===
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 7,551: Line 7,605:  
! Description
 
! Description
 
|-
 
|-
−
| 0-23
+
| colspan="2" | '''DATA0:'''
−
| float1.7.16, Vertex attribute element 1
+
|-
 +
| 0-7
 +
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
 +
|-
 +
| 8-31
 +
| float1.7.16, Vertex attribute element 4 (W)
 +
|-
 +
| colspan="2" | '''DATA1:'''
 
|-
 
|-
−
| 24-31
+
| 0-15
−
| float1.7.16, Vertex attribute element 2 (lower 8 bits)
+
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
−
|}
  −
 
  −
Accepts the first part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
  −
 
  −
=== GPUREG_FIXEDATTRIB_DATA1 ===
  −
 
  −
{| class="wikitable" border="1"
  −
! Bits
  −
! Description
   
|-
 
|-
−
| 0-23
+
| 16-31
−
| float1.7.16, Vertex attribute element 2 (upper 16 bits)
+
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
 
|-
 
|-
−
| 24-31
+
| colspan="2" | '''DATA2:'''
−
| float1.7.16, Vertex attribute element 3 (lower 16 bits)
  −
|}
  −
 
  −
Accepts the second part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
  −
 
  −
=== GPUREG_FIXEDATTRIB_DATA2 ===
  −
 
  −
{| class="wikitable" border="1"
  −
! Bits
  −
! Description
   
|-
 
|-
 
| 0-23
 
| 0-23
−
| float1.7.16, Vertex attribute element 3 (upper 8 bits)
+
| float1.7.16, Vertex attribute element 1 (X)
 
|-
 
|-
 
| 24-31
 
| 24-31
−
| float1.7.16, Vertex attribute element 4
+
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
 
|}
 
|}
   −
Accepts the third part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
+
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
    
=== GPUREG_CMDBUF_SIZE0 ===
 
=== GPUREG_CMDBUF_SIZE0 ===
Line 7,826: Line 7,868:  
|-
 
|-
 
| 0
 
| 0
−
| unsigned, Boolean register b0 value (0 = true, 1 = false)
+
| unsigned, Boolean register b0 value (0 = false, 1 = true)
 
|-
 
|-
 
| 1
 
| 1
−
| unsigned, Boolean register b1 value (0 = true, 1 = false)
+
| unsigned, Boolean register b1 value (0 = false, 1 = true)
 
|-
 
|-
 
| 2
 
| 2
−
| unsigned, Boolean register b2 value (0 = true, 1 = false)
+
| unsigned, Boolean register b2 value (0 = false, 1 = true)
 
|-
 
|-
 
| 3
 
| 3
−
| unsigned, Boolean register b3 value (0 = true, 1 = false)
+
| unsigned, Boolean register b3 value (0 = false, 1 = true)
 
|-
 
|-
 
| 4
 
| 4
−
| unsigned, Boolean register b4 value (0 = true, 1 = false)
+
| unsigned, Boolean register b4 value (0 = false, 1 = true)
 
|-
 
|-
 
| 5
 
| 5
−
| unsigned, Boolean register b5 value (0 = true, 1 = false)
+
| unsigned, Boolean register b5 value (0 = false, 1 = true)
 
|-
 
|-
 
| 6
 
| 6
−
| unsigned, Boolean register b6 value (0 = true, 1 = false)
+
| unsigned, Boolean register b6 value (0 = false, 1 = true)
 
|-
 
|-
 
| 7
 
| 7
−
| unsigned, Boolean register b7 value (0 = true, 1 = false)
+
| unsigned, Boolean register b7 value (0 = false, 1 = true)
 
|-
 
|-
 
| 8
 
| 8
−
| unsigned, Boolean register b8 value (0 = true, 1 = false)
+
| unsigned, Boolean register b8 value (0 = false, 1 = true)
 
|-
 
|-
 
| 9
 
| 9
−
| unsigned, Boolean register b9 value (0 = true, 1 = false)
+
| unsigned, Boolean register b9 value (0 = false, 1 = true)
 
|-
 
|-
 
| 10
 
| 10
−
| unsigned, Boolean register b10 value (0 = true, 1 = false)
+
| unsigned, Boolean register b10 value (0 = false, 1 = true)
 
|-
 
|-
 
| 11
 
| 11
−
| unsigned, Boolean register b11 value (0 = true, 1 = false)
+
| unsigned, Boolean register b11 value (0 = false, 1 = true)
 
|-
 
|-
 
| 12
 
| 12
−
| unsigned, Boolean register b12 value (0 = true, 1 = false)
+
| unsigned, Boolean register b12 value (0 = false, 1 = true)
 
|-
 
|-
 
| 13
 
| 13
−
| unsigned, Boolean register b13 value (0 = true, 1 = false)
+
| unsigned, Boolean register b13 value (0 = false, 1 = true)
 
|-
 
|-
 
| 14
 
| 14
−
| unsigned, Boolean register b14 value (0 = true, 1 = false)
+
| unsigned, Boolean register b14 value (0 = false, 1 = true)
 
|-
 
|-
 
| 15
 
| 15
−
| unsigned, Boolean register b15 value (0 = true, 1 = false)
+
| unsigned, Boolean register b15 value (0 = false, 1 = true)
 
|-
 
|-
 
| 16-31
 
| 16-31
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