Changes

40,303 bytes added , 24 January

Update GPUREG_VSH_COM_MODE from hardware findings

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[[Category:~~GFX~~]]

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[[Category:GPU]]

−

~~(this page is hugely WIP)~~

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

+

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

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In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

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For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

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Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

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The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

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=== Command Header ===

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{| class="wikitable" border="1"

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! Bit

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! Description

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|-

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| 0-15

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| Command ID

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|-

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| 16-19

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| Parameter mask

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|-

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| 20-27

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| Number of extra parameters (may be zero)

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|-

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| 28-30

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| Unused

+

|-

+

| 31

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| Consecutive writing mode

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|}

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=== Parameter masking ===

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Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :

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* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])

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* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])

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* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|GPUREG_GSH_CODETRANSFER_DATA]])

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* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])

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* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

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* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

−

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU ~~Commands]]~~, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#~~GPUREG_VSH_FLOATUNIFORM_CONFIG~~|~~GPUREG_VSH_FLOATUNIFORM_CONFIG~~]] and ever subsequent ones to [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|GPUREG_VSH_FLOATUNIFORM_DATA]]

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It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

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=== Data Types ===

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{| class="wikitable" border="1"

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! Name

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! Description

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|-

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| signed

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| Signed integer

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|-

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| unsigned

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| Unsigned integer

+

|-

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| floatX.Y.Z

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| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits

+

|-

+

| fixedX.Y.Z

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| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits

+

|}

== Register list ==

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| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]

|

−

|

+

|PICA_REG_INTERRUPT

|-

| 0011

Line 392: Line 445:

|-

| 0047

−

| [[#~~GPUREG_0047~~|~~GPUREG_0047~~]]

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| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]

|?

−

|~~PICA_REG_FRAG_OP_CLIP~~

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|PICA_REG_FRAGOP_CLIP

|-

| 0048

−

| [[#~~GPUREG_0048~~|~~GPUREG_0048~~]]

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| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]

|?

−

|~~PICA_REG_FRAG_OP_CLIP_DATA1~~

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|PICA_REG_FRAGOP_CLIP_DATA1

|-

| 0049

−

| [[#~~GPUREG_0049~~|~~GPUREG_0049~~]]

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| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]

|?

−

|~~PICA_REG_FRAG_OP_CLIP_DATA2~~

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|PICA_REG_FRAGOP_CLIP_DATA2

|-

| 004A

−

| [[#~~GPUREG_004A~~|~~GPUREG_004A~~]]

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| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]

|?

−

|~~PICA_REG_FRAG_OP_CLIP_DATA3~~

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|PICA_REG_FRAGOP_CLIP_DATA3

|-

| 004B

−

| [[#~~GPUREG_004B~~|~~GPUREG_004B~~]]

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| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]

|?

−

|~~PICA_REG_FRAG_OP_CLIP_DATA4~~

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|PICA_REG_FRAGOP_CLIP_DATA4

|-

| 004C

Line 424: Line 477:

| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]

| As f24

−

|~~PICA_REG_FRAG_OP_WSCALE_DATA1~~

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|PICA_REG_FRAGOP_WSCALE_DATA1

|-

| 004E

| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]

| As f24

−

|~~PICA_REG_FRAG_OP_WSCALE_DATA2~~

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|PICA_REG_FRAGOP_WSCALE_DATA2

|-

| 004F

Line 437: Line 490:

|-

| 0050

−

| [[#~~GPUREG_SH_OUTMAP_O0~~|GPUREG_SH_OUTMAP_O0]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]

|

|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0

|-

| 0051

−

| [[#~~GPUREG_SH_OUTMAP_O1~~|GPUREG_SH_OUTMAP_O1]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]

|

|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1

|-

| 0052

−

| [[#~~GPUREG_SH_OUTMAP_O2~~|GPUREG_SH_OUTMAP_O2]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]

|

|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2

|-

| 0053

−

| [[#~~GPUREG_SH_OUTMAP_O3~~|GPUREG_SH_OUTMAP_O3]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]

|

|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3

|-

| 0054

−

| [[#~~GPUREG_SH_OUTMAP_O4~~|GPUREG_SH_OUTMAP_O4]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]

|

|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4

|-

| 0055

−

| [[#~~GPUREG_SH_OUTMAP_O5~~|GPUREG_SH_OUTMAP_O5]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]

|

|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5

|-

| 0056

−

| [[#~~GPUREG_SH_OUTMAP_O6~~|GPUREG_SH_OUTMAP_O6]]

+

| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]

|

|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6

Line 522: Line 575:

|-

| 0061

−

| [[#~~GPUREG_0061~~|~~GPUREG_0061~~]]

+

| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]

|?

|PICA_REG_EARLY_DEPTH_FUNC

|-

| 0062

−

| [[#~~GPUREG_0062~~|~~GPUREG_0062~~]]

+

| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]

|?

|PICA_REG_EARLY_DEPTH_TEST1

|-

| 0063

−

| [[#~~GPUREG_0063~~|~~GPUREG_0063~~]]

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| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]

|

−

|

+

|PICA_REG_EARLY_DEPTH_CLEAR

|-

| 0064

−

| [[#~~GPUREG_0064~~|~~GPUREG_0064~~]]

+

| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]

|?

|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE

Line 567: Line 620:

|-

| 006A

−

| [[#~~GPUREG_006A~~|~~GPUREG_006A~~]]

+

| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]

|

|PICA_REG_EARLY_DEPTH_DATA

Line 582: Line 635:

|-

| 006D

−

| [[#~~GPUREG_006D~~|~~GPUREG_006D~~]]

+

| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]

|?

−

|~~PICA_REG_FRAG_OP_WSCALE~~

+

|PICA_REG_FRAGOP_WSCALE

|-

| 006E

−

| [[#~~GPUREG_FRAMEBUFFER_DIM2~~|~~GPUREG_FRAMEBUFFER_DIM2~~]]

+

| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]

|?

|PICA_REG_RENDER_BUF_RESOLUTION1

|-

| 006F

−

| [[#~~GPUREG_006F~~|~~GPUREG_006F~~]]

+

| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]

|?

|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK

Line 686: Line 739:

|-

| 0080

−

| [[#~~GPUREG_TEXUNIT_ENABLE~~|~~GPUREG_TEXUNIT_ENABLE~~]]

+

| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]

|

|PICA_REG_TEXTURE_FUNC

|-

| 0081

−

| [[#~~GPUREG_TEXUNIT0_BORDER_COLOR~~|GPUREG_TEXUNIT0_BORDER_COLOR]]

+

| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]

|

|PICA_REG_TEXTURE0_BORDER_COLOR

|-

| 0082

−

| [[#~~GPUREG_TEXUNIT0_DIM~~|GPUREG_TEXUNIT0_DIM]]

+

| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]

|

|PICA_REG_TEXTURE0_SIZE

|-

| 0083

−

| [[#~~GPUREG_TEXUNIT0_PARAM~~|GPUREG_TEXUNIT0_PARAM]]

+

| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]

|

|PICA_REG_TEXTURE0_WRAP_FILTER

|-

| 0084

−

| [[#~~GPUREG_0084~~|~~GPUREG_0084~~]]

+

| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]

|?

|PICA_REG_TEXTURE0_LOD

|-

| 0085

−

| [[#~~GPUREG_TEXUNIT0_LOC~~|~~GPUREG_TEXUNIT0_LOC~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]

|

|PICA_REG_TEXTURE0_ADDR1

|-

| 0086

−

| [[#~~GPUREG_0086~~|~~GPUREG_0086~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]

|

|PICA_REG_TEXTURE0_ADDR2

|-

| 0087

−

| [[#~~GPUREG_0087~~|~~GPUREG_0087~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]

|

|PICA_REG_TEXTURE0_ADDR3

|-

| 0088

−

| [[#~~GPUREG_0088~~|~~GPUREG_0088~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]

|

|PICA_REG_TEXTURE0_ADDR4

|-

| 0089

−

| [[#~~GPUREG_0089~~|~~GPUREG_0089~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]

|

|PICA_REG_TEXTURE0_ADDR5

|-

| 008A

−

| [[#~~GPUREG_008A~~|~~GPUREG_008A~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]

|

|PICA_REG_TEXTURE0_ADDR6

|-

| 008B

−

| [[#~~GPUREG_008B~~|~~GPUREG_008B~~]]

+

| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]

|?

|PICA_REG_TEXTURE0_SHADOW

Line 756: Line 809:

|-

| 008E

−

| [[#~~GPUREG_TEXUNIT0_TYPE~~|GPUREG_TEXUNIT0_TYPE]]

+

| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]

|?

|PICA_REG_TEXTURE0_FORMAT

|-

| 008F

−

| [[#~~GPUREG_GPUREG_LIGHTING_ENABLE0~~|GPUREG_LIGHTING_ENABLE0]]

+

| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]

|?

|PICA_REG_FRAG_LIGHT_EN0

Line 771: Line 824:

|-

| 0091

−

| [[#~~GPUREG_TEXUNIT1_BORDER_COLOR~~|GPUREG_TEXUNIT1_BORDER_COLOR]]

+

| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]

|

|PICA_REG_TEXTURE1_BORDER_COLOR

|-

| 0092

−

| [[#~~GPUREG_TEXUNIT1_DIM~~|GPUREG_TEXUNIT1_DIM]]

+

| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]

|

|PICA_REG_TEXTURE1_SIZE

|-

| 0093

−

| [[#~~GPUREG_TEXUNIT1_PARAM~~|GPUREG_TEXUNIT1_PARAM]]

+

| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]

|

|PICA_REG_TEXTURE1_WRAP_FILTER

|-

| 0094

−

| [[#~~GPUREG_0094~~|~~GPUREG_0094~~]]

+

| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]

|?

|PICA_REG_TEXTURE1_LOD

|-

| 0095

−

| [[#~~GPUREG_TEXUNIT1_LOC~~|~~GPUREG_TEXUNIT1_LOC~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]

|

|PICA_REG_TEXTURE1_ADDR

|-

| 0096

−

| [[#~~GPUREG_TEXUNIT1_TYPE~~|GPUREG_TEXUNIT1_TYPE]]

+

| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]

|

|PICA_REG_TEXTURE1_FORMAT

Line 811: Line 864:

|-

| 0099

−

| [[#~~GPUREG_TEXUNIT2_BORDER_COLOR~~|GPUREG_TEXUNIT2_BORDER_COLOR]]

+

| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]

|

|PICA_REG_TEXTURE2_BORDER_COLOR

|-

| 009A

−

| [[#~~GPUREG_TEXUNIT2_DIM~~|GPUREG_TEXUNIT2_DIM]]

+

| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]

|

|PICA_REG_TEXTURE2_SIZE

|-

| 009B

−

| [[#~~GPUREG_TEXUNIT2_PARAM~~|GPUREG_TEXUNIT2_PARAM]]

+

| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]

|

|PICA_REG_TEXTURE2_WRAP_FILTER

|-

| 009C

−

| [[#~~GPUREG_009C~~|~~GPUREG_009C~~]]

+

| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]

|?

|PICA_REG_TEXTURE2_LOD

|-

| 009D

−

| [[#~~GPUREG_TEXUNIT2_LOC~~|~~GPUREG_TEXUNIT2_LOC~~]]

+

| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]

|

|PICA_REG_TEXTURE2_ADDR

|-

| 009E

−

| [[#~~GPUREG_TEXUNIT2_TYPE~~|GPUREG_TEXUNIT2_TYPE]]

+

| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]

|

|PICA_REG_TEXTURE2_FORMAT

Line 886: Line 939:

|-

| 00A8

−

| [[#~~GPUREG_00A8~~|~~GPUREG_00A8~~]]

+

| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]

|?

−

|~~PICA_REG_TEXTURE3_PROTEX0~~

+

|PICA_REG_TEXTURE3_PROCTEX0

|-

| 00A9

−

| [[#~~GPUREG_00A9~~|~~GPUREG_00A9~~]]

+

| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]

|?

−

|~~PICA_REG_TEXTURE3_PROTEX1~~

+

|PICA_REG_TEXTURE3_PROCTEX1

|-

| 00AA

−

| [[#~~GPUREG_00AA~~|~~GPUREG_00AA~~]]

+

| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]

|?

−

|~~PICA_REG_TEXTURE3_PROTEX2~~

+

|PICA_REG_TEXTURE3_PROCTEX2

|-

| 00AB

−

| [[#~~GPUREG_00AB~~|~~GPUREG_00AB~~]]

+

| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]

|?

−

|~~PICA_REG_TEXTURE3_PROTEX3~~

+

|PICA_REG_TEXTURE3_PROCTEX3

|-

| 00AC

−

| [[#~~GPUREG_00AC~~|~~GPUREG_00AC~~]]

+

| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]

|?

−

|~~PICA_REG_TEXTURE3_PROTEX4~~

+

|PICA_REG_TEXTURE3_PROCTEX4

|-

| 00AD

−

| [[#~~GPUREG_00AD~~|~~GPUREG_00AD~~]]

+

| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]

|?

−

|~~PICA_REG_TEXTURE3_PROTEX5~~

+

|PICA_REG_TEXTURE3_PROCTEX5

|-

| 00AE

Line 921: Line 974:

|-

| 00AF

−

| [[#~~GPUREG_00AF~~|~~GPUREG_00AF~~]]

+

| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]

|?

−

|~~PICA_REG_PROTEX_LUT~~

+

|PICA_REG_PROCTEX_LUT

|-

| 00B0

−

| [[#~~GPUREG_00B0~~|~~GPUREG_00B0~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA0~~

+

|PICA_REG_PROCTEX_LUT_DATA0

|-

| 00B1

−

| [[#~~GPUREG_00B1~~|~~GPUREG_00B1~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA1~~

+

|PICA_REG_PROCTEX_LUT_DATA1

|-

| 00B2

−

| [[#~~GPUREG_00B2~~|~~GPUREG_00B2~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA2~~

+

|PICA_REG_PROCTEX_LUT_DATA2

|-

| 00B3

−

| [[#~~GPUREG_00B3~~|~~GPUREG_00B3~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA3~~

+

|PICA_REG_PROCTEX_LUT_DATA3

|-

| 00B4

−

| [[#~~GPUREG_00B4~~|~~GPUREG_00B4~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA4~~

+

|PICA_REG_PROCTEX_LUT_DATA4

|-

| 00B5

−

| [[#~~GPUREG_00B5~~|~~GPUREG_00B5~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA5~~

+

|PICA_REG_PROCTEX_LUT_DATA5

|-

| 00B6

−

| [[#~~GPUREG_00B6~~|~~GPUREG_00B6~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA6~~

+

|PICA_REG_PROCTEX_LUT_DATA6

|-

| 00B7

−

| [[#~~GPUREG_00B7~~|~~GPUREG_00B7~~]]

+

| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]

| ?

−

|~~PICA_REG_PROTEX_LUT_DATA7~~

+

|PICA_REG_PROCTEX_LUT_DATA7

|-

| 00B8

Line 1,006: Line 1,059:

|-

| 00C0

−

| [[#~~GPUREG_TEXENV0_SOURCE~~|GPUREG_TEXENV0_SOURCE]]

+

| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]

|

|PICA_REG_TEX_ENV_0

|-

| 00C1

−

| [[#~~GPUREG_TEXENV0_OPERAND~~|GPUREG_TEXENV0_OPERAND]]

+

| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]

|

|PICA_REG_TEX_ENV_0_OPERAND

|-

| 00C2

−

| [[#~~GPUREG_TEXENV0_COMBINER~~|GPUREG_TEXENV0_COMBINER]]

+

| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]

|

|PICA_REG_TEX_ENV_0_COMBINE

|-

| 00C3

−

| [[#~~GPUREG_TEXENV0_COLOR~~|GPUREG_TEXENV0_COLOR]]

+

| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]

|

|PICA_REG_TEX_ENV_0_COLOR

|-

| 00C4

−

| [[#~~GPUREG_TEXENV0_SCALE~~|GPUREG_TEXENV0_SCALE]]

+

| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]

|

|PICA_REG_TEX_ENV_0_SCALE

Line 1,046: Line 1,099:

|-

| 00C8

−

| [[#~~GPUREG_TEXENV1_SOURCE~~|GPUREG_TEXENV1_SOURCE]]

+

| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]

|

|PICA_REG_TEX_ENV_1

|-

| 00C9

−

| [[#~~GPUREG_TEXENV1_OPERAND~~|GPUREG_TEXENV1_OPERAND]]

+

| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]

|

|PICA_REG_TEX_ENV_1_OPERAND

|-

| 00CA

−

| [[#~~GPUREG_TEXENV1_COMBINER~~|GPUREG_TEXENV1_COMBINER]]

+

| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]

|

|PICA_REG_TEX_ENV_1_COMBINE

|-

| 00CB

−

| [[#~~GPUREG_TEXENV1_COLOR~~|GPUREG_TEXENV1_COLOR]]

+

| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]

|

|PICA_REG_TEX_ENV_1_COLOR

|-

| 00CC

−

| [[#~~GPUREG_TEXENV1_SCALE~~|GPUREG_TEXENV1_SCALE]]

+

| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]

|

|PICA_REG_TEX_ENV_1_SCALE

Line 1,086: Line 1,139:

|-

| 00D0

−

| [[#~~GPUREG_TEXENV2_SOURCE~~|GPUREG_TEXENV2_SOURCE]]

+

| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]

|

|PICA_REG_TEX_ENV_2

|-

| 00D1

−

| [[#~~GPUREG_TEXENV2_OPERAND~~|GPUREG_TEXENV2_OPERAND]]

+

| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]

|

|PICA_REG_TEX_ENV_2_OPERAND

|-

| 00D2

−

| [[#~~GPUREG_TEXENV2_COMBINER~~|GPUREG_TEXENV2_COMBINER]]

+

| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]

|

|PICA_REG_TEX_ENV_2_COMBINE

|-

| 00D3

−

| [[#~~GPUREG_TEXENV2_COLOR~~|GPUREG_TEXENV2_COLOR]]

+

| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]

|

|PICA_REG_TEX_ENV_2_COLOR

|-

| 00D4

−

| [[#~~GPUREG_TEXENV2_SCALE~~|GPUREG_TEXENV2_SCALE]]

+

| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]

|

|PICA_REG_TEX_ENV_2_SCALE

Line 1,126: Line 1,179:

|-

| 00D8

−

| [[#~~GPUREG_TEXENV3_SOURCE~~|GPUREG_TEXENV3_SOURCE]]

+

| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]

|

|PICA_REG_TEX_ENV_3

|-

| 00D9

−

| [[#~~GPUREG_TEXENV3_OPERAND~~|GPUREG_TEXENV3_OPERAND]]

+

| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]

|

|PICA_REG_TEX_ENV_3_OPERAND

|-

| 00DA

−

| [[#~~GPUREG_TEXENV3_COMBINER~~|GPUREG_TEXENV3_COMBINER]]

+

| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]

|

|PICA_REG_TEX_ENV_3_COMBINE

|-

| 00DB

−

| [[#~~GPUREG_TEXENV3_COLOR~~|GPUREG_TEXENV3_COLOR]]

+

| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]

|

|PICA_REG_TEX_ENV_3_COLOR

|-

| 00DC

−

| [[#~~GPUREG_TEXENV3_SCALE~~|GPUREG_TEXENV3_SCALE]]

+

| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]

|

|PICA_REG_TEX_ENV_3_SCALE

Line 1,171: Line 1,224:

|-

| 00E1

−

| [[#~~GPUREG_00E1~~|~~GPUREG_00E1~~]]

+

| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]

|?

|PICA_REG_FOG_COLOR

Line 1,186: Line 1,239:

|-

| 00E4

−

| [[#~~GPUREG_00E4~~|~~GPUREG_00E4~~]]

+

| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]

|?

|PICA_REG_GAS_ATTENUATION

|-

| 00E5

−

| [[#~~GPUREG_00E5~~|~~GPUREG_00E5~~]]

+

| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]

|?

|PICA_REG_GAS_ACCMAX

|-

| 00E6

−

| [[#~~GPUREG_00E6~~|~~GPUREG_00E6~~]]

+

| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]

|?

|PICA_REG_FOG_LUT_INDEX

Line 1,206: Line 1,259:

|-

| 00E8

−

| [[#~~GPUREG_00E8~~|~~GPUREG_00E8~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]

|?

|PICA_REG_FOG_LUT_DATA0

|-

| 00E9

−

| [[#~~GPUREG_00E9~~|~~GPUREG_00E9~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]

|?

|PICA_REG_FOG_LUT_DATA1

|-

| 00EA

−

| [[#~~GPUREG_00EA~~|~~GPUREG_00EA~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]

|?

|PICA_REG_FOG_LUT_DATA2

|-

| 00EB

−

| [[#~~GPUREG_00EB~~|~~GPUREG_00EB~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]

|?

|PICA_REG_FOG_LUT_DATA3

|-

| 00EC

−

| [[#~~GPUREG_00EC~~|~~GPUREG_00EC~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]

|?

|PICA_REG_FOG_LUT_DATA4

|-

| 00ED

−

| [[#~~GPUREG_00ED~~|~~GPUREG_00ED~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]

|?

|PICA_REG_FOG_LUT_DATA5

|-

| 00EE

−

| [[#~~GPUREG_00EE~~|~~GPUREG_00EE~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]

|?

|PICA_REG_FOG_LUT_DATA6

|-

| 00EF

−

| [[#~~GPUREG_00EF~~|~~GPUREG_00EF~~]]

+

| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]

|?

|PICA_REG_FOG_LUT_DATA7

|-

| 00F0

−

| [[#~~GPUREG_TEXENV4_SOURCE~~|GPUREG_TEXENV4_SOURCE]]

+

| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]

|

|PICA_REG_TEX_ENV_4

|-

| 00F1

−

| [[#~~GPUREG_TEXENV4_OPERAND~~|GPUREG_TEXENV4_OPERAND]]

+

| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]

|

|PICA_REG_TEX_ENV_4_OPERAND

|-

| 00F2

−

| [[#~~GPUREG_TEXENV4_COMBINER~~|GPUREG_TEXENV4_COMBINER]]

+

| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]

|

|PICA_REG_TEX_ENV_4_COMBINE

|-

| 00F3

−

| [[#~~GPUREG_TEXENV4_COLOR~~|GPUREG_TEXENV4_COLOR]]

+

| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]

|

|PICA_REG_TEX_ENV_4_COLOR

|-

| 00F4

−

| [[#~~GPUREG_TEXENV4_SCALE~~|GPUREG_TEXENV4_SCALE]]

+

| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]

|

|PICA_REG_TEX_ENV_4_SCALE

Line 1,286: Line 1,339:

|-

| 00F8

−

| [[#~~GPUREG_TEXENV5_SOURCE~~|GPUREG_TEXENV5_SOURCE]]

+

| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]

|

|PICA_REG_TEX_ENV_5

|-

| 00F9

−

| [[#~~GPUREG_TEXENV5_OPERAND~~|GPUREG_TEXENV5_OPERAND]]

+

| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]

|

|PICA_REG_TEX_ENV_5_OPERAND

|-

| 00FA

−

| [[#~~GPUREG_TEXENV5_COMBINER~~|GPUREG_TEXENV5_COMBINER]]

+

| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]

|

|PICA_REG_TEX_ENV_5_COMBINE

|-

| 00FB

−

| [[#~~GPUREG_TEXENV5_COLOR~~|GPUREG_TEXENV5_COLOR]]

+

| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]

|

|PICA_REG_TEX_ENV_5_COLOR

|-

| 00FC

−

| [[#~~GPUREG_TEXENV5_SCALE~~|GPUREG_TEXENV5_SCALE]]

+

| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]

|

|PICA_REG_TEX_ENV_5_SCALE

Line 1,335: Line 1,388:

|-

| 0100

−

| [[#~~GPUREG_BLEND_ENABLE~~|~~GPUREG_BLEND_ENABLE~~]]

+

| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]

|

|PICA_REG_COLOR_OPERATION

|-

| 0101

−

| [[#~~GPUREG_BLEND_CONFIG~~|~~GPUREG_BLEND_CONFIG~~]]

+

| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]

|

|PICA_REG_BLEND_FUNC

|-

| 0102

−

| [[#~~GPUREG_LOGICOP_CONFIG~~|~~GPUREG_LOGICOP_CONFIG~~]]

+

| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]

|

|PICA_REG_LOGIC_OP

Line 1,355: Line 1,408:

|-

| 0104

−

| [[#~~GPUREG_ALPHATEST_CONFIG~~|~~GPUREG_ALPHATEST_CONFIG~~]]

+

| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]

|

−

|~~PICA_REG_FRAG_OP_ALPHA_TEST~~

+

|PICA_REG_FRAGOP_ALPHA_TEST

|-

| 0105

Line 1,365: Line 1,418:

|-

| 0106

−

| [[#~~GPUREG_STENCIL_ACTION~~|~~GPUREG_STENCIL_ACTION~~]]

+

| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]

|

|PICA_REG_STENCIL_OP

|-

| 0107

−

| [[#~~GPUREG_DEPTHTEST_CONFIG~~|~~GPUREG_DEPTHTEST_CONFIG~~]]

+

| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]

|

|PICA_REG_DEPTH_COLOR_MASK

Line 1,455: Line 1,508:

|-

| 0118

−

| [[#~~GPUREG_0118~~|~~GPUREG_0118~~]]

+

| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]

|?

|PICA_REG_EARLY_DEPTH_TEST2

Line 1,495: Line 1,548:

|-

| 0120

−

| [[#~~GPUREG_0120~~|~~GPUREG_0120~~]]

+

| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]

|?

|PICA_REG_GAS_LIGHT_XY

|-

| 0121

−

| [[#~~GPUREG_0121~~|~~GPUREG_0121~~]]

+

| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]

|?

|PICA_REG_GAS_LIGHT_Z

|-

| 0122

−

| [[#~~GPUREG_0122~~|~~GPUREG_0122~~]]

+

| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]

|?

|PICA_REG_GAS_LIGHT_Z_COLOR

|-

| 0123

−

| [[#~~GPUREG_0123~~|~~GPUREG_0123~~]]

+

| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]

|?

|PICA_REG_GAS_LUT_INDEX

|-

| 0124

−

| [[#~~GPUREG_0124~~|~~GPUREG_0124~~]]

+

| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]

|?

|PICA_REG_GAS_LUT_DATA

Line 1,525: Line 1,578:

|-

| 0126

−

| [[#~~GPUREG_0126~~|~~GPUREG_0126~~]]

+

| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]

|?

|PICA_REG_GAS_DELTAZ_DEPTH

Line 1,575: Line 1,628:

|-

| 0130

−

| [[#~~GPUREG_0130~~|~~GPUREG_0130~~]]

+

| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]

|?

−

|~~PICA_REG_FRAG_OP_SHADOW~~

+

|PICA_REG_FRAGOP_SHADOW

|-

| 0131

Line 1,664: Line 1,717:

|-

| 0140

−

| [[#~~GPUREG_LIGHTx_SPECULARy~~|GPUREG_LIGHT0_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START

|-

| 0141

−

| [[#~~GPUREG_LIGHTx_SPECULARy~~|GPUREG_LIGHT0_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT0_SPECULAR1

|-

| 0142

−

| [[#~~GPUREG_LIGHTx_DIFFUSE~~|GPUREG_LIGHT0_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT0_DIFFUSE

|-

| 0143

−

| [[#~~GPUREG_LIGHTx_AMBIENT~~|GPUREG_LIGHT0_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT0_AMBIENT

|-

| 0144

−

| [[#~~GPUREG_LIGHTx_XY~~|GPUREG_LIGHT0_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]

|?

|PICA_REG_FRAG_LIGHT0_POSITION_XY

|-

| 0145

−

| [[#~~GPUREG_LIGHTx_Z~~|GPUREG_LIGHT0_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]

|?

|PICA_REG_FRAG_LIGHT0_POSITION_Z

|-

| 0146

−

| [[#~~GPUREG_LIGHTx_SPOTDIR_XY~~|GPUREG_LIGHT0_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT0_SPOT_XY

|-

| 0147

−

| [[#~~GPUREG_LIGHTx_SPOTDIR_Z~~|GPUREG_LIGHT0_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT0_SPOT_Z

Line 1,709: Line 1,762:

|-

| 0149

−

| [[#~~GPUREG_LIGHTx_CONFIG~~|GPUREG_LIGHT0_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]

|

|PICA_REG_FRAG_LIGHT0_TYPE

|-

| 014A

−

| [[#~~GPUREG_LIGHTx_ATTENUATION_BIAS~~|GPUREG_LIGHT0_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]

|?

|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS

|-

| 014B

−

| [[#~~GPUREG_LIGHTx_ATTENUATION_SCALE~~|GPUREG_LIGHT0_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]

|?

|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE

Line 1,744: Line 1,797:

|-

| 0150

−

| [[#~~GPUREG_0150~~|GPUREG_LIGHT1_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT1_SPECULAR0

|-

| 0151

−

| [[#~~GPUREG_0151~~|GPUREG_LIGHT1_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT1_SPECULAR1

|-

| 0152

−

| [[#~~GPUREG_0152~~|GPUREG_LIGHT1_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT1_DIFFUSE

|-

| 0153

−

| [[#~~GPUREG_0153~~|GPUREG_LIGHT1_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT1_AMBIENT

|-

| 0154

−

| [[#~~GPUREG_0154~~|GPUREG_LIGHT1_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]

|?

|PICA_REG_FRAG_LIGHT1_POSITION_XY

|-

| 0155

−

| [[#~~GPUREG_0155~~|GPUREG_LIGHT1_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]

|?

|PICA_REG_FRAG_LIGHT1_POSITION_Z

|-

| 0156

−

| [[#~~GPUREG_0156~~|GPUREG_LIGHT1_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT1_SPOT_XY

|-

| 0157

−

| [[#~~GPUREG_0157~~|GPUREG_LIGHT1_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT1_SPOT_Z

Line 1,789: Line 1,842:

|-

| 0159

−

| [[#~~GPUREG_0159~~|GPUREG_LIGHT1_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT1_TYPE

|-

| 015A

−

| [[#~~GPUREG_015A~~|GPUREG_LIGHT1_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]

|?

|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS

|-

| 015B

−

| [[#~~GPUREG_015B~~|GPUREG_LIGHT1_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]

|?

|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE

Line 1,824: Line 1,877:

|-

| 0160

−

| [[#~~GPUREG_0160~~|GPUREG_LIGHT2_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT2_SPECULAR0

|-

| 0161

−

| [[#~~GPUREG_0161~~|GPUREG_LIGHT2_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT2_SPECULAR1

|-

| 0162

−

| [[#~~GPUREG_0162~~|GPUREG_LIGHT2_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT2_DIFFUSE

|-

| 0163

−

| [[#~~GPUREG_0163~~|GPUREG_LIGHT2_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT2_AMBIENT

|-

| 0164

−

| [[#~~GPUREG_0164~~|GPUREG_LIGHT2_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]

|?

|PICA_REG_FRAG_LIGHT2_POSITION_XY

|-

| 0165

−

| [[#~~GPUREG_0165~~|GPUREG_LIGHT2_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]

|?

|PICA_REG_FRAG_LIGHT2_POSITION_Z

|-

| 0166

−

| [[#~~GPUREG_0166~~|GPUREG_LIGHT2_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT2_SPOT_XY

|-

| 0167

−

| [[#~~GPUREG_0167~~|GPUREG_LIGHT2_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT2_SPOT_Z

Line 1,869: Line 1,922:

|-

| 0169

−

| [[#~~GPUREG_0169~~|GPUREG_LIGHT2_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT2_TYPE

|-

| 016A

−

| [[#~~GPUREG_016A~~|GPUREG_LIGHT2_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]

|?

|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS

|-

| 016B

−

| [[#~~GPUREG_016B~~|GPUREG_LIGHT2_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]

|?

|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE

Line 1,904: Line 1,957:

|-

| 0170

−

| [[#~~GPUREG_0170~~|GPUREG_LIGHT3_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT3_SPECULAR0

|-

| 0171

−

| [[#~~GPUREG_0171~~|GPUREG_LIGHT3_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT3_SPECULAR1

|-

| 0172

−

| [[#~~GPUREG_0172~~|GPUREG_LIGHT3_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT3_DIFFUSE

|-

| 0173

−

| [[#~~GPUREG_0173~~|GPUREG_LIGHT3_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT3_AMBIENT

|-

| 0174

−

| [[#~~GPUREG_0174~~|GPUREG_LIGHT3_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]

|?

|PICA_REG_FRAG_LIGHT3_POSITION_XY

|-

| 0175

−

| [[#~~GPUREG_0175~~|GPUREG_LIGHT3_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]

|?

|PICA_REG_FRAG_LIGHT3_POSITION_Z

|-

| 0176

−

| [[#~~GPUREG_0176~~|GPUREG_LIGHT3_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT3_SPOT_XY

|-

| 0177

−

| [[#~~GPUREG_0177~~|GPUREG_LIGHT3_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT3_SPOT_Z

Line 1,949: Line 2,002:

|-

| 0179

−

| [[#~~GPUREG_0179~~|GPUREG_LIGHT3_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT3_TYPE

|-

| 017A

−

| [[#~~GPUREG_017A~~|GPUREG_LIGHT3_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]

|?

|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS

|-

| 017B

−

| [[#~~GPUREG_017B~~|GPUREG_LIGHT3_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]

|?

|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE

Line 1,984: Line 2,037:

|-

| 0180

−

| [[#~~GPUREG_0180~~|GPUREG_LIGHT4_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT4_SPECULAR0

|-

| 0181

−

| [[#~~GPUREG_0181~~|GPUREG_LIGHT4_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT4_SPECULAR1

|-

| 0182

−

| [[#~~GPUREG_0182~~|GPUREG_LIGHT4_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT4_DIFFUSE

|-

| 0183

−

| [[#~~GPUREG_0183~~|GPUREG_LIGHT4_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT4_AMBIENT

|-

| 0184

−

| [[#~~GPUREG_0184~~|GPUREG_LIGHT4_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]

|?

|PICA_REG_FRAG_LIGHT4_POSITION_XY

|-

| 0185

−

| [[#~~GPUREG_0185~~|GPUREG_LIGHT4_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]

|?

|PICA_REG_FRAG_LIGHT4_POSITION_Z

|-

| 0186

−

| [[#~~GPUREG_0186~~|GPUREG_LIGHT4_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT4_SPOT_XY

|-

| 0187

−

| [[#~~GPUREG_0187~~|GPUREG_LIGHT4_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT4_SPOT_Z

Line 2,029: Line 2,082:

|-

| 0189

−

| [[#~~GPUREG_0189~~|GPUREG_LIGHT4_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT4_TYPE

|-

| 018A

−

| [[#~~GPUREG_018A~~|GPUREG_LIGHT4_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]

|?

|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS

|-

| 018B

−

| [[#~~GPUREG_018B~~|GPUREG_LIGHT4_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]

|?

|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE

Line 2,064: Line 2,117:

|-

| 0190

−

| [[#~~GPUREG_0190~~|GPUREG_LIGHT5_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT5_SPECULAR0

|-

| 0191

−

| [[#~~GPUREG_0191~~|GPUREG_LIGHT5_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT5_SPECULAR1

|-

| 0192

−

| [[#~~GPUREG_0192~~|GPUREG_LIGHT5_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT5_DIFFUSE

|-

| 0193

−

| [[#~~GPUREG_0193~~|GPUREG_LIGHT5_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT5_AMBIENT

|-

| 0194

−

| [[#~~GPUREG_0194~~|GPUREG_LIGHT5_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]

|?

|PICA_REG_FRAG_LIGHT5_POSITION_XY

|-

| 0195

−

| [[#~~GPUREG_0195~~|GPUREG_LIGHT5_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]

|?

|PICA_REG_FRAG_LIGHT5_POSITION_Z

|-

| 0196

−

| [[#~~GPUREG_0196~~|GPUREG_LIGHT5_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT5_SPOT_XY

|-

| 0197

−

| [[#~~GPUREG_0197~~|GPUREG_LIGHT5_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT5_SPOT_Z

Line 2,109: Line 2,162:

|-

| 0199

−

| [[#~~GPUREG_0199~~|GPUREG_LIGHT5_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT5_TYPE

|-

| 019A

−

| [[#~~GPUREG_019A~~|GPUREG_LIGHT5_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]

|

−

|

+

|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS

|-

| 019B

−

| [[#~~GPUREG_019B~~|GPUREG_LIGHT5_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]

|

−

|

+

|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE

|-

| 019C

Line 2,144: Line 2,197:

|-

| 01A0

−

| [[#~~GPUREG_01A0~~|GPUREG_LIGHT6_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT6_SPECULAR0

|-

| 01A1

−

| [[#~~GPUREG_01A1~~|GPUREG_LIGHT6_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT6_SPECULAR1

|-

| 01A2

−

| [[#~~GPUREG_01A2~~|GPUREG_LIGHT6_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]

|

|PICA_REG_FRAG_LIGHT6_DIFFUSE

|-

| 01A3

−

| [[#~~GPUREG_01A3~~|GPUREG_LIGHT6_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]

|

|PICA_REG_FRAG_LIGHT6_AMBIENT

|-

| 01A4

−

| [[#~~GPUREG_01A4~~|GPUREG_LIGHT6_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]

|

|PICA_REG_FRAG_LIGHT6_POSITION_XY

|-

| 01A5

−

| [[#~~GPUREG_01A5~~|GPUREG_LIGHT6_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]

|

|PICA_REG_FRAG_LIGHT6_POSITION_Z

|-

| 01A6

−

| [[#~~GPUREG_01A6~~|GPUREG_LIGHT6_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT6_SPOT_XY

|-

| 01A7

−

| [[#~~GPUREG_01A7~~|GPUREG_LIGHT6_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT6_SPOT_Z

Line 2,189: Line 2,242:

|-

| 01A9

−

| [[#~~GPUREG_01A9~~|GPUREG_LIGHT6_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT6_TYPE

|-

| 01AA

−

| [[#~~GPUREG_01AA~~|GPUREG_LIGHT6_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]

|

−

|

+

|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS

|-

| 01AB

−

| [[#~~GPUREG_01AB~~|GPUREG_LIGHT6_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]

|

−

|

+

|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE

|-

| 01AC

Line 2,224: Line 2,277:

|-

| 01B0

−

| [[#~~GPUREG_01B0~~|GPUREG_LIGHT7_SPECULAR0]]

+

| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]

|?

|PICA_REG_FRAG_LIGHT7_SPECULAR0

|-

| 01B1

−

| [[#~~GPUREG_01B1~~|GPUREG_LIGHT7_SPECULAR1]]

+

| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]

|?

|PICA_REG_FRAG_LIGHT7_SPECULAR1

|-

| 01B2

−

| [[#~~GPUREG_01B2~~|GPUREG_LIGHT7_DIFFUSE]]

+

| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]

|?

|PICA_REG_FRAG_LIGHT7_DIFFUSE

|-

| 01B3

−

| [[#~~GPUREG_01B3~~|GPUREG_LIGHT7_AMBIENT]]

+

| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]

|?

|PICA_REG_FRAG_LIGHT7_AMBIENT

|-

| 01B4

−

| [[#~~GPUREG_01B4~~|GPUREG_LIGHT7_XY]]

+

| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]

|?

|PICA_REG_FRAG_LIGHT7_POSITION_XY

|-

| 01B5

−

| [[#~~GPUREG_01B5~~|GPUREG_LIGHT7_Z]]

+

| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]

|?

|PICA_REG_FRAG_LIGHT7_POSITION_Z

|-

| 01B6

−

| [[#~~GPUREG_01B6~~|GPUREG_LIGHT7_SPOTDIR_XY]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]

|?

|PICA_REG_FRAG_LIGHT7_SPOT_XY

|-

| 01B7

−

| [[#~~GPUREG_01B7~~|GPUREG_LIGHT7_SPOTDIR_Z]]

+

| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]

|?

|PICA_REG_FRAG_LIGHT7_SPOT_Z

Line 2,269: Line 2,322:

|-

| 01B9

−

| [[#~~GPUREG_01B9~~|GPUREG_LIGHT7_CONFIG]]

+

| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]

|?

|PICA_REG_FRAG_LIGHT7_TYPE

|-

| 01BA

−

| [[#~~GPUREG_01BA~~|GPUREG_LIGHT7_ATTENUATION_BIAS]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]

|

−

|

+

|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS

|-

| 01BB

−

| [[#~~GPUREG_01BB~~|GPUREG_LIGHT7_ATTENUATION_SCALE]]

+

| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]

|

−

|

+

|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE

|-

| 01BC

Line 2,344: Line 2,397:

|-

| 01C8

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA0

|-

| 01C9

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA1

|-

| 01CA

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA2

|-

| 01CB

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA3

|-

| 01CC

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA4

|-

| 01CD

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA5

|-

| 01CE

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA6

|-

| 01CF

−

| [[#~~GPUREG_LIGHTING_LUT_DATA~~|~~GPUREG_LIGHTING_LUT_DATA~~]]

+

| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]

|?

|PICA_REG_FRAG_LIGHT_LUT_DATA7

Line 2,648: Line 2,701:

|-

| 0203

−

| [[#~~GPUREG_ATTRIBBUFFER0_OFFSET~~|GPUREG_ATTRIBBUFFER0_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]

|

|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET

|-

| 0204

−

| [[#~~GPUREG_ATTRIBBUFFER0_CONFIG1~~|GPUREG_ATTRIBBUFFER0_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]

|

|PICA_REG_LOAD_ARRAY0_ELEMENT0

|-

| 0205

−

| [[#~~GPUREG_ATTRIBBUFFER0_CONFIG2~~|GPUREG_ATTRIBBUFFER0_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]

|

|PICA_REG_LOAD_ARRAY0_ELEMENT1

|-

| 0206

−

| [[#~~GPUREG_ATTRIBBUFFER1_OFFSET~~|GPUREG_ATTRIBBUFFER1_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]

|

|-

| 0207

−

| [[#~~GPUREG_ATTRIBBUFFER1_CONFIG1~~|GPUREG_ATTRIBBUFFER1_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]

|

|-

| 0208

−

| [[#~~GPUREG_ATTRIBBUFFER1_CONFIG2~~|GPUREG_ATTRIBBUFFER1_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]

|

|-

| 0209

−

| [[#~~GPUREG_ATTRIBBUFFER2_OFFSET~~|GPUREG_ATTRIBBUFFER2_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]

|

|-

| 020A

−

| [[#~~GPUREG_ATTRIBBUFFER2_CONFIG1~~|GPUREG_ATTRIBBUFFER2_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]

|

|-

| 020B

−

| [[#~~GPUREG_ATTRIBBUFFER2_CONFIG2~~|GPUREG_ATTRIBBUFFER2_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]

|

|-

| 020C

−

| [[#~~GPUREG_ATTRIBBUFFER3_OFFSET~~|GPUREG_ATTRIBBUFFER3_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]

|

|-

| 020D

−

| [[#~~GPUREG_ATTRIBBUFFER3_CONFIG1~~|GPUREG_ATTRIBBUFFER3_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]

|

|-

| 020E

−

| [[#~~GPUREG_ATTRIBBUFFER3_CONFIG2~~|GPUREG_ATTRIBBUFFER3_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]

|

|-

| 020F

−

| [[#~~GPUREG_ATTRIBBUFFER4_OFFSET~~|GPUREG_ATTRIBBUFFER4_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]

|

|-

| 0210

−

| [[#~~GPUREG_ATTRIBBUFFER4_CONFIG1~~|GPUREG_ATTRIBBUFFER4_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]

|

|-

| 0211

−

| [[#~~GPUREG_ATTRIBBUFFER4_CONFIG2~~|GPUREG_ATTRIBBUFFER4_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]

|

|-

| 0212

−

| [[#~~GPUREG_ATTRIBBUFFER5_OFFSET~~|GPUREG_ATTRIBBUFFER5_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]

|

|-

| 0213

−

| [[#~~GPUREG_ATTRIBBUFFER5_CONFIG1~~|GPUREG_ATTRIBBUFFER5_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]

|

|-

| 0214

−

| [[#~~GPUREG_ATTRIBBUFFER5_CONFIG2~~|GPUREG_ATTRIBBUFFER5_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]

|

|-

| 0215

−

| [[#~~GPUREG_ATTRIBBUFFER6_OFFSET~~|GPUREG_ATTRIBBUFFER6_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]

|

|-

| 0216

−

| [[#~~GPUREG_ATTRIBBUFFER6_CONFIG1~~|GPUREG_ATTRIBBUFFER6_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]

|

|-

| 0217

−

| [[#~~GPUREG_ATTRIBBUFFER6_CONFIG2~~|GPUREG_ATTRIBBUFFER6_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]

|

|-

| 0218

−

| [[#~~GPUREG_ATTRIBBUFFER7_OFFSET~~|GPUREG_ATTRIBBUFFER7_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]

|

|-

| 0219

−

| [[#~~GPUREG_ATTRIBBUFFER7_CONFIG1~~|GPUREG_ATTRIBBUFFER7_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]

|

|-

| 021A

−

| [[#~~GPUREG_ATTRIBBUFFER7_CONFIG2~~|GPUREG_ATTRIBBUFFER7_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]

|

|-

| 021B

−

| [[#~~GPUREG_ATTRIBBUFFER8_OFFSET~~|GPUREG_ATTRIBBUFFER8_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]

|

|-

| 021C

−

| [[#~~GPUREG_ATTRIBBUFFER8_CONFIG1~~|GPUREG_ATTRIBBUFFER8_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]

|

|-

| 021D

−

| [[#~~GPUREG_ATTRIBBUFFER8_CONFIG2~~|GPUREG_ATTRIBBUFFER8_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]

|

|-

| 021E

−

| [[#~~GPUREG_ATTRIBBUFFER9_OFFSET~~|GPUREG_ATTRIBBUFFER9_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]

|

|-

| 021F

−

| [[#~~GPUREG_ATTRIBBUFFER9_CONFIG1~~|GPUREG_ATTRIBBUFFER9_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]

|

|-

| 0220

−

| [[#~~GPUREG_ATTRIBBUFFER9_CONFIG2~~|GPUREG_ATTRIBBUFFER9_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]

|

|-

| 0221

−

| [[#~~GPUREG_ATTRIBBUFFER10_OFFSET~~|GPUREG_ATTRIBBUFFER10_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]

|

|-

| 0222

−

| [[#~~GPUREG_ATTRIBBUFFER10_CONFIG1~~|GPUREG_ATTRIBBUFFER10_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]

|

|-

| 0223

−

| [[#~~GPUREG_ATTRIBBUFFER10_CONFIG2~~|GPUREG_ATTRIBBUFFER10_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]

|

|-

| 0224

−

| [[#~~GPUREG_ATTRIBBUFFER11_OFFSET~~|GPUREG_ATTRIBBUFFER11_OFFSET]]

+

| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]

|

|-

| 0225

−

| [[#~~GPUREG_ATTRIBBUFFER11_CONFIG1~~|GPUREG_ATTRIBBUFFER11_CONFIG1]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]

|

|-

| 0226

−

| [[#~~GPUREG_ATTRIBBUFFER11_CONFIG2~~|GPUREG_ATTRIBBUFFER11_CONFIG2]]

+

| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]

|

Line 2,858: Line 2,911:

|-

| 022D

−

| [[#~~GPUREG_022D~~|~~GPUREG_022D~~]]

+

| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]

|

−

|

+

|PICA_REG_POST_VERTEX_CACHE_NUM

|-

| 022E

Line 2,878: Line 2,931:

|-

| 0231

−

| [[#~~GPUREG_0231~~|~~GPUREG_0231~~]]

+

| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]

|?

|PICA_REG_VTX_FUNC

Line 2,888: Line 2,941:

|-

| 0233

−

| [[#~~GPUREG_FIXEDATTRIB_DATA~~|~~GPUREG_FIXEDATTRIB_DATA~~]]

+

| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]

|?

|PICA_REG_VS_FIXED_ATTR_DATA0

|-

| 0234

−

| [[#~~GPUREG_FIXEDATTRIB_DATA~~|~~GPUREG_FIXEDATTRIB_DATA~~]]

+

| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]

|?

|PICA_REG_VS_FIXED_ATTR_DATA1

|-

| 0235

−

| [[#~~GPUREG_FIXEDATTRIB_DATA~~|~~GPUREG_FIXEDATTRIB_DATA~~]]

+

| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]

|?

|PICA_REG_VS_FIXED_ATTR_DATA2

Line 2,915: Line 2,968:

| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]

|

−

|

+

|PICA_REG_COMMAND_BUF_SIZE_CH0

|-

| 0239

| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]

|

−

|

+

|PICA_REG_COMMAND_BUF_SIZE_CH1

|-

| 023A

| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]

|

−

|

+

|PICA_REG_COMMAND_BUF_ADDR_CH0

|-

| 023B

| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]

|

−

|

+

|PICA_REG_COMMAND_BUF_ADDR_CH1

|-

| 023C

| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]

|

−

|

+

|PICA_REG_COMMAND_BUF_KICK_CH0

|-

| 023D

| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]

|

−

|

+

|PICA_REG_COMMAND_BUF_KICK_CH1

|-

| 023E

Line 2,963: Line 3,016:

|-

| 0242

−

| [[#~~GPUREG_0242~~|~~GPUREG_0242~~]]

+

| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]

|?

|PICA_REG_VS_ATTR_NUM1

Line 2,973: Line 3,026:

|-

| 0244

−

| [[#~~GPUREG_0244~~|~~GPUREG_0244~~]]

+

| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]

|?

|PICA_REG_VS_COM_MODE

|-

| 0245

−

| [[#~~GPUREG_0245~~|~~GPUREG_0245~~]]

+

| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]

|?

|PICA_REG_START_DRAW_FUNC0

Line 3,003: Line 3,056:

|-

| 024A

−

| [[#~~GPUREG_024A~~|~~GPUREG_024A~~]]

+

| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]

|?

|PICA_REG_VS_OUT_REG_NUM1

Line 3,038: Line 3,091:

|-

| 0251

−

| [[#~~GPUREG_0251~~|~~GPUREG_0251~~]]

+

| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]

|?

|PICA_REG_VS_OUT_REG_NUM2

|-

| 0252

−

| [[#~~GPUREG_0252~~|~~GPUREG_0252~~]]

+

| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]

|?

|PICA_REG_GS_MISC_REG0

|-

| 0253

−

| [[#~~GPUREG_0253~~|~~GPUREG_0253~~]]

+

| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]

|?

|PICA_REG_DRAW_MODE1

|-

| 0254

−

| [[#~~GPUREG_0254~~|~~GPUREG_0254~~]]

+

| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]

|?

|PICA_REG_GS_MISC_REG1

Line 3,105: Line 3,158:

| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]

| ?

−

|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_VS_OUT_REG_NUM3

+

|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3

|-

| 025F

Line 3,284: Line 3,337:

|-

| 0280

−

| [[#~~GPUREG_GSH_BOOLUNIFORM~~|GPUREG_GSH_BOOLUNIFORM]]

+

| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]

|

|PICA_REG_GS_BOOL

|-

| 0281

−

| [[#~~GPUREG_GSH_INTUNIFORM_I0~~|GPUREG_GSH_INTUNIFORM_I0]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]

|

|PICA_REG_GS_INT0

|-

| 0282

−

| [[#~~GPUREG_GSH_INTUNIFORM_I1~~|GPUREG_GSH_INTUNIFORM_I1]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]

|

|PICA_REG_GS_INT1

|-

| 0283

−

| [[#~~GPUREG_GSH_INTUNIFORM_I2~~|GPUREG_GSH_INTUNIFORM_I2]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]

|

|PICA_REG_GS_INT2

|-

| 0284

−

| [[#~~GPUREG_GSH_INTUNIFORM_I3~~|GPUREG_GSH_INTUNIFORM_I3]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]

|

|PICA_REG_GS_INT3

Line 3,329: Line 3,382:

|-

| 0289

−

| [[#~~GPUREG_GSH_INPUTBUFFER_CONFIG~~|GPUREG_GSH_INPUTBUFFER_CONFIG]]

+

| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]

|

|PICA_REG_GS_ATTR_NUM

|-

| 028A

−

| [[#~~GPUREG_GSH_ENTRYPOINT~~|GPUREG_GSH_ENTRYPOINT]]

+

| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]

|

|PICA_REG_GS_START_ADDR

|-

| 028B

−

| [[#~~GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW~~|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]

+

| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]

|

|PICA_REG_GS_ATTR_IN_REG_MAP0

|-

| 028C

−

| [[#~~GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH~~|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]

+

| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]

|

|PICA_REG_GS_ATTR_IN_REG_MAP1

|-

| 028D

−

| [[#~~GPUREG_GSH_OUTMAP_MASK~~|GPUREG_GSH_OUTMAP_MASK]]

+

| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]

|

|PICA_REG_GS_OUT_REG_MASK

Line 3,359: Line 3,412:

|-

| 028F

−

| [[#~~GPUREG_GSH_CODETRANSFER_END~~|GPUREG_GSH_CODETRANSFER_END]]

+

| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]

|

|PICA_REG_GS_PROG_RENEWAL_END

|-

| 0290

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_CONFIG~~|~~GPUREG_GSH_FLOATUNIFORM_CONFIG~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]

|

|PICA_REG_GS_FLOAT_ADDR

|-

| 0291

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_INDEX~~|~~GPUREG_GSH_FLOATUNIFORM_INDEX~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]

|

−

|~~PICA_REG_GS_FLOAT_DATA1~~

+

|PICA_REG_GS_FLOAT_DATA0

|-

| 0292

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]

|

−

|~~PICA_REG_GS_FLOAT_DATA2~~

+

|PICA_REG_GS_FLOAT_DATA1

|-

| 0293

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]

|

−

|~~PICA_REG_GS_FLOAT_DATA3~~

+

|PICA_REG_GS_FLOAT_DATA2

|-

| 0294

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]

|

−

|~~PICA_REG_GS_FLOAT_DATA4~~

+

|PICA_REG_GS_FLOAT_DATA3

|-

| 0295

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]

|

−

|~~PICA_REG_GS_FLOAT_DATA5~~

+

|PICA_REG_GS_FLOAT_DATA4

|-

| 0296

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]

|

−

|~~PICA_REG_GS_FLOAT_DATA6~~

+

|PICA_REG_GS_FLOAT_DATA5

|-

| 0297

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]

|

−

|~~PICA_REG_GS_FLOAT_DATA7~~

+

|PICA_REG_GS_FLOAT_DATA6

|-

| 0298

−

| [[#~~GPUREG_GSH_FLOATUNIFORM_DATA~~|~~GPUREG_GSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]

|

−

|~~PICA_REG_GS_FLOAT_DATA8~~

+

|PICA_REG_GS_FLOAT_DATA7

|-

| 0299

Line 3,419: Line 3,472:

|-

| 029B

−

| [[#~~GPUREG_GSH_CODETRANSFER_INDEX~~|GPUREG_GSH_CODETRANSFER_INDEX]]

+

| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]

| ?

|PICA_REG_GS_PROG_ADDR

|-

| 029C

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]

|

|PICA_REG_GS_PROG_DATA0

|-

| 029D

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]

|

|PICA_REG_GS_PROG_DATA1

|-

| 029E

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]

|

|PICA_REG_GS_PROG_DATA2

|-

| 029F

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]

|

|PICA_REG_GS_PROG_DATA3

|-

| 02A0

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]

|

|PICA_REG_GS_PROG_DATA4

|-

| 02A1

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]

|

|PICA_REG_GS_PROG_DATA5

|-

| 02A2

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]

|

|PICA_REG_GS_PROG_DATA6

|-

| 02A3

−

| [[#~~GPUREG_GSH_CODETRANSFER_DATA~~|~~GPUREG_GSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]

|

|PICA_REG_GS_PROG_DATA7

Line 3,469: Line 3,522:

|-

| 02A5

−

| [[#~~GPUREG_GSH_OPDESCS_INDEX~~|GPUREG_GSH_OPDESCS_INDEX]]

+

| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]

|

|PICA_REG_GS_PROG_SWIZZLE_ADDR

|-

| 02A6

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA0

|-

| 02A7

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA1

|-

| 02A8

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA2

|-

| 02A9

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA3

|-

| 02AA

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA4

|-

| 02AB

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA5

|-

| 02AC

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA6

|-

| 02AD

−

| [[#~~GPUREG_GSH_OPDESCS_DATA~~|~~GPUREG_GSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]

|

|PICA_REG_GS_PROG_SWIZZLE_DATA7

Line 3,526: Line 3,579:

|-

| 02B0

−

| [[#~~GPUREG_VSH_BOOLUNIFORM~~|GPUREG_VSH_BOOLUNIFORM]]

+

| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]

|

|PICA_REG_VS_BOOL

|-

| 02B1

−

| [[#~~GPUREG_VSH_INTUNIFORM_I0~~|GPUREG_VSH_INTUNIFORM_I0]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]

|

|PICA_REG_VS_INT0

|-

| 02B2

−

| [[#~~GPUREG_VSH_INTUNIFORM_I1~~|GPUREG_VSH_INTUNIFORM_I1]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]

|

|PICA_REG_VS_INT1

|-

| 02B3

−

| [[#~~GPUREG_VSH_INTUNIFORM_I2~~|GPUREG_VSH_INTUNIFORM_I2]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]

|

|PICA_REG_VS_INT2

|-

| 02B4

−

| [[#~~GPUREG_VSH_INTUNIFORM_I3~~|GPUREG_VSH_INTUNIFORM_I3]]

+

| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]

|

|PICA_REG_VS_INT3

Line 3,571: Line 3,624:

|-

| 02B9

−

| [[#~~GPUREG_VSH_INPUTBUFFER_CONFIG~~|GPUREG_VSH_INPUTBUFFER_CONFIG]]

+

| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]

|

|PICA_REG_VS_ATTR_NUM0

|-

| 02BA

−

| [[#~~GPUREG_VSH_ENTRYPOINT~~|GPUREG_VSH_ENTRYPOINT]]

+

| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]

|

|PICA_REG_VS_START_ADDR

|-

| 02BB

−

| [[#~~GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW~~|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]

+

| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]

|

|PICA_REG_VS_ATTR_IN_REG_MAP0

|-

| 02BC

−

| [[#~~GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH~~|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]

+

| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]

|

|PICA_REG_VS_ATTR_IN_REG_MAP1

|-

| 02BD

−

| [[#~~GPUREG_VSH_OUTMAP_MASK~~|GPUREG_VSH_OUTMAP_MASK]]

+

| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]

|

|PICA_REG_VS_OUT_REG_MASK

Line 3,601: Line 3,654:

|-

| 02BF

−

| [[#~~GPUREG_VSH_CODETRANSFER_END~~|GPUREG_VSH_CODETRANSFER_END]]

+

| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]

|

|PICA_REG_VS_PROG_RENEWAL_END

|-

| 02C0

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_INDEX~~|GPUREG_VSH_FLOATUNIFORM_INDEX]]

+

| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]

|

|PICA_REG_VS_FLOAT_ADDR

|-

| 02C1

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]

|

−

|~~PICA_REG_VS_FLOAT_DATA1~~

+

|PICA_REG_VS_FLOAT_DATA0

|-

| 02C2

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]

|

−

|~~PICA_REG_VS_FLOAT_DATA2~~

+

|PICA_REG_VS_FLOAT_DATA1

|-

| 02C3

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]

|

−

|~~PICA_REG_VS_FLOAT_DATA3~~

+

|PICA_REG_VS_FLOAT_DATA2

|-

| 02C4

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]

|

−

|~~PICA_REG_VS_FLOAT_DATA4~~

+

|PICA_REG_VS_FLOAT_DATA3

|-

| 02C5

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]

|

−

|~~PICA_REG_VS_FLOAT_DATA5~~

+

|PICA_REG_VS_FLOAT_DATA4

|-

| 02C6

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]

|

−

|~~PICA_REG_VS_FLOAT_DATA6~~

+

|PICA_REG_VS_FLOAT_DATA5

|-

| 02C7

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]

|

−

|~~PICA_REG_VS_FLOAT_DATA7~~

+

|PICA_REG_VS_FLOAT_DATA6

|-

| 02C8

−

| [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]

+

| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]

|

−

|~~PICA_REG_VS_FLOAT_DATA8~~

+

|PICA_REG_VS_FLOAT_DATA7

|-

| 02C9

Line 3,661: Line 3,714:

|-

| 02CB

−

| [[#~~GPUREG_VSH_CODETRANSFER_INDEX~~|GPUREG_VSH_CODETRANSFER_INDEX]]

+

| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]

| ?

|PICA_REG_VS_PROG_ADDR

|-

| 02CC

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]

|

|PICA_REG_VS_PROG_DATA0

|-

| 02CD

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]

|

|PICA_REG_VS_PROG_DATA1

|-

| 02CE

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]

|

|PICA_REG_VS_PROG_DATA2

|-

| 02CF

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]

|

|PICA_REG_VS_PROG_DATA3

|-

| 02D0

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]

|

|PICA_REG_VS_PROG_DATA4

|-

| 02D1

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]

|

|PICA_REG_VS_PROG_DATA5

|-

| 02D2

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]

|

|PICA_REG_VS_PROG_DATA6

|-

| 02D3

−

| [[#~~GPUREG_VSH_CODETRANSFER_DATA~~|~~GPUREG_VSH_CODETRANSFER_DATA~~]]

+

| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]

|

|PICA_REG_VS_PROG_DATA7

Line 3,711: Line 3,764:

|-

| 02D5

−

| [[#~~GPUREG_VSH_OPDESCS_INDEX~~|GPUREG_VSH_OPDESCS_INDEX]]

+

| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]

| ?

|PICA_REG_VS_PROG_SWIZZLE_ADDR

|-

| 02D6

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA0

|-

| 02D7

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA1

|-

| 02D8

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA2

|-

| 02D9

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA3

|-

| 02DA

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA4

|-

| 02DB

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA5

|-

| 02DC

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA6

|-

| 02DD

−

| [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]]

+

| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]

|

|PICA_REG_VS_PROG_SWIZZLE_DATA7

Line 3,938: Line 3,991:

=== GPUREG_FINALIZE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)

+

|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.

Line 3,944: Line 4,005:

== Rasterizer registers ==

−

== ~~Texturing registers~~ ==

+

=== GPUREG_FACECULLING_CONFIG ===

−

== ~~Framebuffer registers ==~~

+

{| class="wikitable" border="1"

−

+

! Bits

−

~~=== GPUREG_FRAMEBUFFER_INVALIDATE ===~~

+

! Description

−

+

|-

−

~~Writing~~ 1 ~~to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache~~, ~~so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.~~

+

| 0-1

−

+

| unsigned, Culling mode

−

~~=== GPUREG_FRAMEBUFFER_FLUSH ===~~

+

|}

−

~~Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.~~

−

~~=== GPUREG_DEPTHBUFFER_FORMAT ===~~

+

This register is used to configure the face culling mode.

−

~~The format the current depth buffer should be written into. Following~~ values ~~are possible~~:

+

Culling mode values:

{| class="wikitable" border="1"

Line 3,965: Line 4,024:

|-

| 0

−

| ~~16-bit depth~~

+

| None

|-

| 1

−

| ~~?? seems to freeze the GPU~~

+

| Front Face (Counter Clockwise)

|-

| 2

−

| ~~24-bit depth~~

+

| Back Face (Counter Clockwise)

+

|}

+

=== GPUREG_VIEWPORT_WIDTH ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 3

+

| 0-23

−

| ~~24-bit depth + 8-bit stencil (stencil is within bit 24-31)~~

+

| float1.7.16, width / 2

|}

−

~~=== GPUREG_COLORBUFFER_FORMAT ===~~

+

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

−

~~Describes the format of the current color buffer used for 3D rendering.~~

+

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"

Line 3,985: Line 4,051:

! Description

|-

−

| ~~0-7~~

+

| 1-31

−

~~| Pixel size (0=16-bit,~~ 1~~=24-bit, 2=32-bit, 3=64~~-~~bit?)~~

+

| float1.7.23, 2 / width

−

|-

−

~~| 16-~~23

−

~~| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8~~, 2~~=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).~~

−

~~Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].~~

−

~~Color components are laid out in reverse byte order, with the most significant bits used first.~~

|}

−

~~=== GPUREG_FRAMEBUFFER_BLOCK32 ===~~

+

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

−

When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

+

=== GPUREG_VIEWPORT_HEIGHT ===

−

== ~~Fragment lighting registers ==~~

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-23

+

| float1.7.16, height / 2

+

|}

−

~~=== GPUREG_LIGHTING_ENABLE0 ===~~

+

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

−

~~This register is set to 0 when fragment lighting is disabled, and to 1 when it is enabled.~~

+

=== GPUREG_VIEWPORT_INVH ===

−

==~~= GPUREG_LIGHTING_ENABLE1 ===~~

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 1-31

+

| float1.7.23, 2 / height

+

|}

−

This register is ~~set~~ to ~~1 when fragment lighting is disabled~~, ~~and to 0 when it is enabled~~.

+

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

−

=== ~~GPUREG_LIGHTING_CONFIG0~~ ===

+

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"

Line 4,016: Line 4,088:

|-

| 0

−

| ~~Shadow factor enable~~, ~~usually set~~ to ~~bit16 OR bit18 OR bit19~~

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

+

|}

+

This register is used to enable clipping planes.

+

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 1

+

| 0-23

−

| ~~Unknown~~, ~~set~~ to 0

+

| float1.7.16, Clipping plane coefficient ''i''

+

|}

+

This register is used to configure clipping plane coefficients.

+

=== GPUREG_DEPTHMAP_SCALE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 2-3

+

| 0-23

−

| ~~"Fresnel selector" (see below)~~

+

| float1.7.16, Near - Far

−

|-

+

|}

−

~~| 4-7~~

+

−

| "~~Config~~", "~~Light env config~~" ~~(see below)~~

+

This register is used to configure the depth range scale.

+

=== GPUREG_DEPTHMAP_OFFSET ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 8-15

+

| 0-23

−

| ~~Unknown~~, ~~set~~ to 4

+

| float1.7.16, Near + Polygon Offset

+

|}

+

This register is used to configure the depth range bias.

+

=== GPUREG_SH_OUTMAP_TOTAL ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 16

+

| 0-2

−

~~| "Shadow primary", 0=disabled, 1=enabled~~

+

| unsigned, Number of following attributes

−

|-

−

~~| 17~~

−

~~| "Shadow secondary", 0=disabled, 1=enabled~~

−

|-

−

~~| 18~~

−

~~| "Invert shadow", 0=disabled, 1=enabled~~

−

|-

−

~~| 19~~

−

~~| "Shadow alpha", 0=disabled, 1=enabled~~

−

|-

−

~~| 20-21~~

−

~~| Unknown, set to 0~~

−

|-

−

~~| 22-23~~

−

~~| "Bump selector"~~

−

|-

−

~~| 24-25~~

−

~~| "Shadow selector"~~

−

|-

−

~~| 26~~

−

~~| Unknown, set to~~ 0

−

|-

−

| 27

−

~~| "Clamp highlights", 0=disabled, 1=enabled~~

−

|-

−

~~| 28-29~~

−

~~| "Bump mode", "Light env texy usage" (see below)~~

−

|-

−

~~| 30~~

−

~~| "Bump renorm", 0=enabled, 1=disabled~~

−

|-

−

~~| 31~~

−

~~| Unknown~~, ~~set to 1~~

|}

−

~~Fresnel selector constants:~~

+

This register is used to configure the total shader output map attributes.

+

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"

−

! ~~Value~~

+

! Bits

! Description

|-

−

| 0

+

| 0-4

−

| ~~NO_FRESNEL~~

+

| unsigned, Semantic for the x component of the register.

|-

−

| 1

+

| 8-12

−

| ~~PRI_ALPHA_FRESNEL~~

+

| unsigned, Semantic for the y component of the register.

|-

−

| 2

+

| 16-20

−

| ~~SEC_ALPHA_FRESNEL~~

+

| unsigned, Semantic for the z component of the register.

|-

−

| 3

+

| 24-28

−

| ~~PRI_SEC_ALPHA_FRESNEL~~

+

| unsigned, Semantic for the w component of the register.

|}

−

~~Light env config constants~~:

+

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

+

Semantics that have not been mapped to a component of an output register have a value of 1

+

Semantic values:

{| class="wikitable" border="1"

! Value

+

! Semantic

! Description

|-

−

| 0

+

| 0x00

−

| ~~LIGHT_ENV_LAYER_CONFIG0~~

+

| position.x

+

| rowspan="4" | Vertex Position

|-

−

| 1

+

| 0x01

−

| ~~LIGHT_ENV_LAYER_CONFIG1~~

+

| position.y

|-

−

| 2

+

| 0x02

−

| ~~LIGHT_ENV_LAYER_CONFIG2~~

+

| position.z

+

|-

+

| 0x03

+

| position.w

+

|-

+

| 0x04

+

| normquat.x

+

| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)

+

|-

+

| 0x05

+

| normquat.y

+

|-

+

| 0x06

+

| normquat.z

+

|-

+

| 0x07

+

| normquat.w

+

|-

+

| 0x08

+

| color.r

+

| rowspan="4" | Vertex color

+

|-

+

| 0x09

+

| color.g

+

|-

+

| 0x0A

+

| color.b

+

|-

+

| 0x0B

+

| color.a

+

|-

+

| 0x0C

+

| texcoord0.u

+

| rowspan="2" | Texture coordinates for texture 0

+

|-

+

| 0x0D

+

| texcoord0.v

+

|-

+

| 0x0E

+

| texcoord1.u

+

| rowspan="2" | Texture coordinates for texture 1

+

|-

+

| 0x0F

+

| texcoord1.v

+

|-

+

| 0x10

+

| texcoord0.w

+

|

+

|-

+

| 0x12

+

| view.x

+

| rowspan="3" | View vector (for fragment lighting)

|-

−

| 3

+

| 0x13

−

| ~~LIGHT_ENV_LAYER_CONFIG3~~

+

| view.y

|-

−

| 4

+

| 0x14

−

| ~~LIGHT_ENV_LAYER_CONFIG4~~

+

| view.z

+

|-

−

| 5

+

| 0x16

−

| ~~LIGHT_ENV_LAYER_CONFIG5~~

+

| texcoord2.u

+

| rowspan="2" | Texture coordinates for texture 2

|-

−

| 6

+

| 0x17

−

| ~~LIGHT_ENV_LAYER_CONFIG6~~

+

| texcoord2.v

+

|-

−

| ~~8 (sic)~~

+

| 0x1F

−

| ~~LIGHT_ENV_LAYER_CONFIG7~~

+

| Unused component

+

| Should be set for unused components of the output register

|}

−

~~Bump mode constants:~~

+

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"

−

! ~~Value~~

+

! Bits

! Description

|-

−

| 0

+

| 0-1

−

~~| BUMP_NOT_USED~~

+

| unsigned, Early depth function

−

|-

−

| 1

−

| ~~BUMP_AS_BUMP~~

−

|-

−

~~| 2~~

−

~~| BUMP_AS_TANG~~

|}

−

~~Bit 30 is set when bump mode is not zero~~.

+

This register configures the early depth test function.

−

~~=== GPUREG_LIGHTING_CONFIG1 ===~~

+

Early depth function values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

| 0

−

| ~~Disable bit for frag light source 0 shadows~~

+

| >=

|-

| 1

−

| ~~Disable bit for frag light source 1 shadows~~

+

| >

|-

| 2

−

| ~~Disable bit for frag light source 2 shadows~~

+

| <=

|-

| 3

−

| ~~Disable bit for frag light source 3 shadows~~

+

| <

+

|}

+

=== GPUREG_EARLYDEPTH_TEST1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 4

+

| 0

−

| ~~Disable bit for frag light source 4 shadows~~

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

+

|}

+

This register sets whether the early depth test is enabled.

+

=== GPUREG_EARLYDEPTH_CLEAR ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 5

+

| 0

−

| ~~Disable bit for frag light source 5 shadows~~

+

| unsigned, Trigger (0 = idle, 1 = clear)

+

|}

+

This register triggers clearing the early depth data.

+

=== GPUREG_SH_OUTATTR_MODE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 6

+

| 0

−

| ~~Disable bit for frag light source 6 shadows~~

+

| unsigned, Use texture coordinates (0 = don't use, 1 = use)

+

|}

+

This register is used to configure the shader output attribute mode.

+

=== GPUREG_SCISSORTEST_MODE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 7

+

| 0-1

−

| ~~Disable bit for frag light source 7 shadows~~

+

| unsigned, Enabled (0 = disabled, 3 = enabled)

+

|}

+

This register is used to enable scissor testing.

+

=== GPUREG_SCISSORTEST_POS ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 8

+

| 0-9

−

| ~~Disable bit for frag light source 0 spot~~

+

| unsigned, X1

|-

−

| 9

+

| 16-25

−

| ~~Disable bit for frag light source~~ 1 ~~spot~~

+

| unsigned, Y1

+

|}

+

This register is used to configure the scissor test start position.

+

=== GPUREG_SCISSORTEST_DIM ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 10

+

| 0-9

−

| ~~Disable bit for frag light source 2 spot~~

+

| unsigned, X2

|-

−

| 11

+

| 16-25

−

| ~~Disable bit for frag light source 3 spot~~

+

| unsigned, Y2

+

|}

+

This register is used to configure the scissor test end position.

+

=== GPUREG_VIEWPORT_XY ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 12

+

| 0-9

−

| ~~Disable bit for frag light source 4 spot~~

+

| signed, X

|-

−

| 13

+

| 16-25

−

| ~~Disable bit for frag light source 5 spot~~

+

| signed, Y

+

|}

+

This register is used to configure the viewport position.

+

=== GPUREG_EARLYDEPTH_DATA ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-23

+

| unsigned, Clear value

+

|}

+

This register is used to configure the early depth clear value.

+

=== GPUREG_DEPTHMAP_ENABLE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 14

+

| 0

−

| ~~Disable bit for frag light source 6 spot~~

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

+

|}

+

This register is used to enable depth range.

+

=== GPUREG_RENDERBUF_DIM ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 15

+

| 0-10

−

| ~~Disable bit for frag light source 7 spot~~

+

| unsigned, Width

|-

−

| 16

+

| 12-21

−

| ~~Disable bit for lut_D0~~

+

| unsigned, Height - 1

|-

−

| 17

+

| 24

−

| ~~Disable bit for lut_D1~~

+

| 0x1

+

|}

+

This register is used to configure the output framebuffer dimensions.

+

=== GPUREG_SH_OUTATTR_CLOCK ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 18

+

| 0

−

| ~~Unknown~~, ~~set to~~ 1

+

| unsigned, 'position.z' present (0 = absent, 1 = present)

|-

−

| 19

+

| 1

−

| ~~Disable bit for lut_FR~~

+

| unsigned, 'color' component present (0 = absent, 1 = present)

|-

−

| 20

+

| 8

−

| ~~Disable bit for lut_RB~~

+

| unsigned, 'texcoord0' component present (0 = absent, 1 = present)

|-

−

| 21

+

| 9

−

| ~~Disable bit for lut_RG~~

+

| unsigned, 'texcoord1' component present (0 = absent, 1 = present)

|-

−

| 22

+

| 10

−

| ~~Disable bit for lut_RR~~

+

| unsigned, 'texcoord2' component present (0 = absent, 1 = present)

|-

−

| 23

+

| 16

−

| ~~Unknown~~, ~~set to~~ 1

+

| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)

|-

| 24

−

| ~~Disable bit for frag light source~~ 0 ~~distance attenuation~~

+

| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)

−

|-

+

|}

−

~~| 25~~

−

~~| Disable bit for frag light source~~ 1 ~~distance attenuation~~

−

|-

−

~~| 26~~

−

~~| Disable bit for frag light source 2 distance attenuation~~

−

|-

−

~~| 27~~

−

~~| Disable bit for frag light source 3 distance attenuation~~

−

|-

−

~~| 28~~

−

~~| Disable bit for frag light source 4 distance attenuation~~

−

|-

−

~~| 29~~

−

~~| Disable bit for frag light source 5 distance attenuation~~

−

|-

−

~~| 30~~

−

~~| Disable bit for frag light source 6 distance attenuation~~

−

|-

−

~~| 31~~

−

~~| Disable bit for frag light source 7 distance attenuation~~

−

|}

−

~~=== GPUREG_LIGHTING_NUM_LIGHTS ===~~

+

This register controls the clock supply to parts relating to certain attributes.

−

~~The number of active lights (0..8) are written to this register.~~

+

== Texturing registers ==

−

=== ~~GPUREG_LIGHTING_LIGHT_PERMUTATION~~ ===

+

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"

Line 4,248: Line 4,457:

! Description

|-

−

| 0-2

+

| 0

−

| ~~ID of the 1st~~ enabled ~~light~~ (0~~..7~~)

+

| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 1

+

| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 2

+

| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)

|-

−

| ~~4-6~~

+

| 3

−

| ~~ID of the 2nd enabled light (0..7)~~

+

| 0x0

|-

−

| 8-10

+

| 8-9

−

| ~~ID of the 3rd enabled light (0..7)~~

+

| unsigned, Texture 3 coordinates

|-

−

| ~~12-14~~

+

| 10

−

| ~~ID of the 4th~~ enabled ~~light~~ (0~~..7~~)

+

| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)

|-

−

| ~~16-18~~

+

| 12

−

| ~~ID of the 5th enabled light (0..7)~~

+

| 0x1

|-

−

| ~~20-22~~

+

| 13

−

| ~~ID of the 6th enabled light (0..7)~~

+

| unsigned, Texture 2 coordinates

|-

−

| ~~24-26~~

+

| 16

−

| ~~ID of the 7th enabled light~~ (0~~..7~~)

+

| unsigned, Clear texture cache (0 = don't clear, 1 = clear)

|-

−

| 28-30

+

| 17-31

−

| ~~ID of the 8th enabled light (0..7)~~

+

| 0x0

|}

−

~~=== GPUREG_LIGHTING_LUTINPUT_SELECT ===~~

+

This register is used to enable texture units.

+

Texture 3 coordinates values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-3

+

| 0

−

| ~~Input selector for lut_D0~~

+

| Texture 0

|-

−

| ~~4-7~~

+

| 1

−

| ~~Input selector for lut_D1~~

+

| Texture 1

|-

−

| ~~8-11~~

+

| 2

−

| ~~Input selector for lut_SP~~

+

| Texture 2

−

|-

+

|}

−

| ~~12-15~~

+

−

~~| Input selector for lut_FR~~

+

Texture 2 coordinates values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

|-

−

| ~~16-19~~

+

| 0

−

| ~~Input selector for lut_RB~~

+

| Texture 2

|-

−

| ~~20-23~~

+

| 1

−

| ~~Input selector for lut_RG~~

+

| Texture 1

−

|-

−

~~| 24-27~~

−

~~| Input selector for lut_RR~~

−

|-

−

~~| 28-31~~

−

~~| Input selector for lut_DA~~

|}

−

~~Input selector values:~~

+

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"

−

! ~~Value~~

+

! Bits

! Description

|-

−

| 0

+

| 0-7

−

| ~~N·H~~

+

| unsigned, Red

|-

−

| 1

+

| 8-15

−

| ~~V·H~~

+

| unsigned, Green

|-

−

| 2

+

| 16-23

−

| ~~N·V~~

+

| unsigned, Blue

|-

−

| 3

+

| 24-31

−

| ~~L·N~~

+

| unsigned, Alpha

+

|}

+

This register is used to set a texture unit's border color.

+

=== GPUREG_TEXUNIT''i''_DIM ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 4

+

| 0-10

−

| ~~-L·P (aka Spotlight aka SP)~~

+

| unsigned, Height

|-

−

| 5

+

| 16-26

−

| ~~cos φ (aka CP)~~

+

| unsigned, Width

|}

−

=== ~~GPUREG_LIGHTING_LUTINPUT_ABS~~ ===

+

This register is used to set a texture unit's dimensions.

+

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"

! Bits

! Description

−

|-

−

~~| 0~~

−

~~| abs() flag for the input of lut_D0 (0=enabled, 1=disabled)~~

|-

| 1

−

| ~~abs() flag for the input of lut_D1 (0=enabled~~, ~~1=disabled)~~

+

| unsigned, Magnification filter

|-

| 2

−

| ~~abs() flag for the input of lut_SP (0=enabled~~, ~~1=disabled)~~

+

| unsigned, Minification filter

|-

−

| 3

+

| 4-5

−

| ~~abs() flag for the input of lut_FR~~ (0=~~enabled~~, 1=~~disabled~~)

+

| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4

|-

−

| 4

+

| 8-10

−

| ~~abs() flag for the input of lut_RB (0=enabled~~, ~~1=disabled)~~

+

| unsigned, Wrap T

|-

−

| 5

+

| 12-14

−

| ~~abs() flag for the input of lut_RG (0=enabled~~, ~~1=disabled)~~

+

| unsigned, Wrap S

|-

−

| 6

+

| 16-17

−

| ~~abs() flag for the input of lut_RR (0=enabled, 1=disabled)~~

+

| 0x0

|-

−

| 7

+

| 20

−

| ~~abs() flag for the input of lut_DA~~ (0=~~enabled~~, 1=~~disabled~~)

+

| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)

+

|-

+

| 24

+

| unsigned, Mipmap filter

+

|-

+

| 28-30

+

| unsigned, Type (Texture 0 only)

|}

−

This register ~~controls whether the absolute value of the input~~ is ~~taken before using~~ a ~~LUT~~.

+

This register is used to set a texture unit's extra parameters.

−

~~=== GPUREG_LIGHTING_LUTINPUT_SCALE ===~~

+

Filter values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-3

+

| 0

−

| ~~Scaler selector for lut_D0~~

+

| Nearest

|-

−

| ~~4-7~~

+

| 1

−

| ~~Scaler selector for lut_D1~~

+

| Linear

+

|}

+

Wrap values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

|-

−

| ~~8-11~~

+

| 0

−

| ~~Scaler selector for lut_SP~~

+

| Clamp to edge

|-

−

| ~~12-15~~

+

| 1

−

| ~~Scaler selector for lut_FR~~

+

| Clamp to border

|-

−

| ~~16-19~~

+

| 2

−

| ~~Scaler selector for lut_RB~~

+

| Repeat

|-

−

| ~~20-23~~

+

| 3

−

| ~~Scaler selector for lut_RG~~

+

| Mirrored repeat

−

|-

−

~~| 24-27~~

−

~~| Scaler selector for lut_RR~~

−

|-

−

~~| 28-31~~

−

~~| Scaler selector for lut_DA~~

|}

−

~~Scaler selector~~ values:

+

Type values:

{| class="wikitable" border="1"

Line 4,400: Line 4,630:

|-

| 0

−

| 1x

+

| 2D

|-

| 1

−

| 2x

+

| Cube map

|-

| 2

−

| 4x

+

| Shadow 2D

|-

| 3

−

| 8x

+

| Projection

|-

−

| 6

+

| 4

−

| ~~0.25x~~

+

| Shadow cube

|-

−

| 7

+

| 5

−

| ~~0.5x~~

+

| Disabled

|}

−

~~This register controls the scaling that is applied to the output (or maybe the input?) of a LUT.~~

+

=== GPUREG_TEXUNIT''i''_LOD ===

−

=== ~~GPUREG_LIGHTING_LUT_INDEX~~ ===

{| class="wikitable" border="1"

Line 4,426: Line 4,654:

! Description

|-

−

| 0-7

+

| 0-12

−

| ~~Starting entry offset (0~~..~~.255)~~

+

| fixed1.4.8, Bias

|-

−

| 8-10

+

| 16-19

−

| ~~LUT ID (context=0) or Light ID (context=1~~,2)

+

| unsigned, Max Level

|-

−

| 11-12

+

| 24-27

−

| ~~Context ID~~

+

| unsigned, Min Level

|}

−

~~LUT ID values:~~

+

This register is used to configure a texture unit's level of detail.

+

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

+

First ADDR register:

{| class="wikitable" border="1"

−

! ~~Value~~

+

! Bits

! Description

|-

−

| 0

+

| 0-27

−

~~| lut_D0~~

+

| unsigned, Texture physical address >> 3

−

|-

−

~~| 1~~

−

~~| lut_D1~~

−

|-

−

| 3

−

~~| lut_FR~~

−

|-

−

~~| 4~~

−

~~| lut_RB~~

−

|-

−

~~| 5~~

−

~~| lut_RG~~

−

|-

−

~~| 6~~

−

~~| lut_RR~~

|}

−

~~Context ID values~~:

+

Subsequent ADDR registers:

−

{| class="wikitable" border="1"

−

! ~~Value~~

+

! Bits

! Description

|-

−

| 0

+

| 0-21

−

~~| LUTs common to all lights - writes to the LUT selected by the ID~~

+

| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)

−

|-

−

~~| 1~~

−

~~| lut_SP - writes to the LUT specific to the selected light~~

−

|-

−

| 2

−

~~| lut_DA - writes to the LUT specific to the selected light~~

|}

−

~~=== GPUREG_LIGHTING_LUT_DATA ===~~

+

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

−

~~Lighting LUT data~~ is ~~written here~~.

−

~~A LUT contains data for the input domain~~ [-1.~~0, 1~~.~~0], which is indexed using a signed 8~~-~~bit number [~~-~~128, 127~~]. ~~Therefore a LUT contains 256 entries. The index of a value~~ is ~~(int)(x/127.0f) & 0xFF~~.

−

~~Format of an entry~~:

+

If the texture is a cube:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Register

! Description

|-

−

| 0-11

+

| ADDR1

−

| ~~Entry value (12bit fractional number; floatval = x / 4096; however 0xFFF is treated as 1.0)~~

+

| Positive X

+

|-

+

| ADDR2

+

| Negative X

+

|-

+

| ADDR3

+

| Positive Y

+

|-

+

| ADDR4

+

| Negative Y

|-

−

| ~~12-22~~

+

| ADDR5

−

| ~~Absolute value of the difference between the next entry and this entry (11bit fractional number; floatval = x / 2048; however 0x7FF is treated as 1.0)~~

+

| Positive Z

|-

−

| 23

+

| ADDR6

−

| ~~Sign bit of the difference (0=positive, 1=negative)~~

+

| Negative Z

|}

−

~~== Geometry pipeline registers ==~~

+

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

−

=== ~~GPUREG_GEOSTAGE_CONFIG~~ ===

+

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"

Line 4,507: Line 4,721:

! Description

|-

−

| 0-7

+

| 0

−

| ~~Geometry stage mode.~~ (0=~~Vertex shader only~~, 2=~~Vertex shader + geometry shader~~)

+

| unsigned, Perspective (0 = perspective, 1 = not perspective)

−

|-

−

~~| 8~~

−

| Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. '''If this is 0, you don't need to use GPU_UNKPRIM with DrawElements.'''

−

|-

−

~~| 9-15~~

−

~~| No effect.~~

−

|-

−

~~| 16-23~~

−

~~| Unknown.~~

|-

−

| 24-31

+

| 1-23

−

| ~~Unknown~~. ~~Often set to~~ 0.

+

| fixed0.0.24, Z bias (upper 23 bits)

|}

−

This register ~~configures the geometry stage of the GPU pipeline~~.

+

This register is used to set a texture unit's shadow texture properties.

−

~~=== GPUREG_FIXEDATTRIB_INDEX ===~~

−

~~See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.~~

+

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"

Line 4,533: Line 4,736:

! Description

|-

−

| 0-31

+

| 0-3

−

| Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to [[#GPUREG_FIXEDATTRIB_DATA|GPUREG_FIXEDATTRIB_DATA]]. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, ~~and writes to the data register will input vertex data directly into the pipeline.~~

+

| unsigned, Format

|}

−

~~=== GPUREG_FIXEDATTRIB_DATA ===~~

+

This register is used to set a texture unit's data format.

−

~~Accepts a packed 4-tuple of float24~~ values (in the same format used for [[#GPUREG_VSH_FLOATUNIFORM_DATA|specifying shader uniforms]]). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]].

+

Format values:

−

~~If immediate~~-~~mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re~~-~~set after each write.~~

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

! GL Format

+

! GL Data Type

+

|-

+

| 0x0

+

| RGBA8888

+

| GL_RGBA

+

| GL_UNSIGNED_BYTE

+

|-

+

| 0x1

+

| RGB888

+

| GL_RGB

+

| GL_UNSIGNED_BYTE

+

|-

+

| 0x2

+

| RGBA5551

+

| GL_RGBA

+

| GL_UNSIGNED_SHORT_5_5_5_1

+

|-

+

| 0x3

+

| RGB565

+

| GL_RGB

+

| GL_UNSIGNED_SHORT_5_6_5

+

|-

+

| 0x4

+

| RGBA4444

+

| GL_RGBA

+

| GL_UNSIGNED_SHORT_4_4_4_4

+

|-

+

| 0x5

+

| IA8

+

| GL_LUMINANCE_ALPHA

+

| GL_UNSIGNED_BYTE

+

|-

+

| 0x6

+

| HILO8

+

|

+

|

+

|-

+

| 0x7

+

| I8

+

| GL_LUMINANCE

+

| GL_UNSIGNED_BYTE

+

|-

+

| 0x8

+

| A8

+

| GL_ALPHA

+

| GL_UNSIGNED_BYTE

+

|-

+

| 0x9

+

| IA44

+

| GL_LUMINANCE_ALPHA

+

| GL_UNSIGNED_BYTE_4_4_EXT

+

|-

+

| 0xA

+

| I4

+

|

+

|

+

|-

+

| 0xB

+

| A4

+

| GL_ALPHA

+

| GL_UNSIGNED_NIBBLE_EXT

+

|-

+

| 0xC

+

| ETC1

+

| GL_ETC1_RGB8_OES

+

|

+

|-

+

| 0xD

+

| ETC1A4

+

|

+

|

+

|}

−

=== ~~GPUREG_RESTART_PRIMITIVE~~ ===

+

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"

Line 4,549: Line 4,827:

! Description

|-

−

| 0-7

+

| 0

−

| ~~Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with [[GPU:Immediate-Mode Vertex Submission|immediate-mode]]~~, ~~but most games seem to write to it before every draw call.~~

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

|}

−

~~== Geometry shader registers ==~~

+

This register is used to enable lighting.

−

=== ~~GPUREG_GSH_BOOLUNIFORM~~ ===

+

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"

Line 4,561: Line 4,839:

! Description

|-

−

| 0

+

| 0-2

−

| ~~Value of geometry shader unit's b0 boolean register. (0=true~~, ~~1=false)~~

+

| unsigned, U-direction clamp

|-

−

| 1

+

| 3-5

−

| ~~Value of geometry shader unit's b1 boolean register. (0=true~~, ~~1=false)~~

+

| unsigned, V-direction clamp

|-

−

| 2

+

| 6-9

−

| ~~Value of geometry shader unit's b2 boolean register. (0=true~~, ~~1=false)~~

+

| unsigned, RGB mapping function

|-

−

| 3

+

| 10-13

−

| ~~Value of geometry shader unit's b3 boolean register. (0=true~~, ~~1=false)~~

+

| unsigned, Alpha mapping function

|-

−

| 4

+

| 14

−

| ~~Value of geometry shader unit's b4 boolean register.~~ (0=~~true~~, 1=~~false~~)

+

| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)

|-

−

| 5

+

| 15

−

| ~~Value of geometry shader unit's b5 boolean register.~~ (0=~~true~~, 1=~~false~~)

+

| unsigned, Noise enabled (0 = disabled, 1 = enabled)

|-

−

| 6

+

| 16-17

−

| ~~Value of geometry shader unit's b6 boolean register. (0=true~~, ~~1=false)~~

+

| unsigned, U-direction shift

|-

−

| 7

+

| 18-19

−

| ~~Value of geometry shader unit's b7 boolean register. (0=true~~, ~~1=false)~~

+

| unsigned, V-direction shift

|-

−

| 8

+

| 20-27

−

| ~~Value of geometry shader~~ unit~~'s b8 boolean register~~. (0=~~true,~~ 1~~=false)~~

+

| float1.5.10, Texture bias (lower 8 bits)

+

|}

+

This register is used to configure the procedural texture unit.

+

Clamp values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

|-

−

| 9

+

| 0

−

| ~~Value of geometry shader unit's b9 boolean register. (0=true, 1=false)~~

+

| Clamp to zero

|-

−

| 10

+

| 1

−

| ~~Value of geometry shader unit's b10 boolean register. (0=true, 1=false)~~

+

| Clamp to edge

|-

−

| 11

+

| 2

−

| ~~Value of geometry shader unit's b11 boolean register. (0=true, 1=false)~~

+

| Symmetrical repeat

|-

−

| 12

+

| 3

−

| ~~Value of geometry shader unit's b12 boolean register. (0=true, 1=false)~~

+

| Mirrored repeat

|-

−

| 13

+

| 4

−

| ~~Value of geometry shader unit's b13 boolean register. (0=true, 1=false)~~

+

| Pulse

−

|-

−

~~| 14~~

−

~~| Value of geometry shader unit's b14 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 15~~

−

~~| Value of geometry shader unit's b15 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 16-31~~

−

~~| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang~~

|}

−

~~This register is used to set the geometry shader unit's boolean registers.~~

+

Mapping function values:

−

~~=== GPUREG_GSH_INTUNIFORM_I0 ===~~

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-7

+

| 0

−

| ~~Value for geometry shader's i0.x~~ (~~u8, 0~~-~~255~~)

+

| U

+

|-

+

| 1

+

| U²

+

|-

+

| 2

+

| V

+

|-

+

| 3

+

| V²

+

|-

+

| 4

+

| (U + V) / 2

+

|-

+

| 5

+

| (U² + V²) / 2

+

|-

+

| 6

+

| sqrt(U² + V²)

|-

−

| ~~8-15~~

+

| 7

−

| ~~Value for geometry shader's i0.y (u8, 0-255)~~

+

| Minimum

|-

−

| ~~16-23~~

+

| 8

−

| ~~Value for geometry shader's i0.z (u8, 0-255)~~

+

| Maximum

|-

−

| ~~24-31~~

+

| 9

−

| ~~Value for geometry shader's i0.w (u8, 0-255)~~

+

| Rmax

|}

−

~~This register is used to set the geometry shader's i0 integer register.~~

+

Shift values:

−

~~=== GPUREG_GSH_INTUNIFORM_I1 ===~~

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-7

+

| 0

−

| ~~Value for geometry shader's i1.x (u8, 0-255)~~

+

| None

|-

−

| ~~8-15~~

+

| 1

−

| ~~Value for geometry shader's i1.y (u8, 0-255)~~

+

| Odd

|-

−

| ~~16-23~~

+

| 2

−

| ~~Value for geometry shader's i1.z (u8, 0-255)~~

+

| Even

−

|-

−

~~| 24-31~~

−

~~| Value for geometry shader's i1.w (u8, 0-255)~~

|}

−

~~This register is used to set the geometry shader's i1 integer register.~~

+

=== GPUREG_TEXUNIT3_PROCTEX1 ===

−

=== ~~GPUREG_GSH_INTUNIFORM_I2~~ ===

{| class="wikitable" border="1"

Line 4,663: Line 4,950:

! Description

|-

−

| 0-7

+

| 0-15

−

| ~~Value for geometry shader's i2~~.~~x (u8~~, 0-~~255)~~

+

| fixed1.3.12, U-direction noise amplitude

|-

−

~~| 8-15~~

+

| 16-31

−

~~| Value for geometry shader's i2.y (u8, 0-255)~~

+

| float1.5.10, U-direction noise phase

−

|-

−

| 16-23

−

| ~~Value for geometry shader's i2~~.~~z (u8, 0-255)~~

−

|-

−

~~| 24-31~~

−

~~| Value for geometry shader's i2~~.~~w (u8~~, 0-~~255)~~

|}

−

This register is used to ~~set~~ the ~~geometry shader~~'s ~~i2 integer register~~.

+

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

−

=== ~~GPUREG_GSH_INTUNIFORM_I3~~ ===

+

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"

Line 4,684: Line 4,965:

! Description

|-

−

| 0-7

+

| 0-15

−

| ~~Value for geometry shader's i3~~.~~x (u8~~, 0-~~255)~~

+

| fixed1.3.12, V-direction noise amplitude

|-

−

~~| 8-15~~

+

| 16-31

−

~~| Value for geometry shader's i3.y (u8, 0-255)~~

+

| float1.5.10, V-direction noise phase

−

|-

−

| 16-23

−

| ~~Value for geometry shader's i3~~.~~z (u8, 0-255)~~

−

|-

−

~~| 24-31~~

−

~~| Value for geometry shader's i3~~.~~w (u8~~, 0-~~255)~~

|}

−

This register is used to ~~set~~ the ~~geometry shader~~'s ~~i3 integer register~~.

+

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

−

=== ~~GPUREG_GSH_INPUTBUFFER_CONFIG~~ ===

+

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"

Line 4,705: Line 4,980:

! Description

|-

−

| 0-7

+

| 0-15

−

| ~~Input buffer stride minus 1~~, ~~in float vec4 registers. (value 0 means a stride of 1 float vec4 register)~~

+

| float1.5.10, U-direction noise frequency

|-

−

| 8-23

+

| 16-31

−

| ~~Unknown~~. ~~These bits typically aren't updated by games~~.

+

| float1.5.10, V-direction noise frequency

−

|-

−

~~| 24-31~~

−

~~| Unknown. This is typically set to 8 for geometry shaders.~~

|}

−

This register is used to configure the ~~geometry shader~~'s ~~input buffer~~. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.

+

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

−

=== ~~GPUREG_GSH_ENTRYPOINT~~ ===

+

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"

Line 4,724: Line 4,995:

! Description

|-

−

| 0-15

+

| 0-2

−

| ~~Geometry shader unit entrypoint~~, ~~in words.~~

+

| unsigned, Minification filter

+

|-

+

| 3-6

+

| Min LOD (usually 0)

+

|-

+

| 7-10

+

| Max LOD (usually 6)

+

|-

+

| 11-18

+

| unsigned, Texture width

|-

−

| 16-31

+

| 19-26

−

| ~~Unknown~~. ~~This seems to always be set to 0x7FFF~~, ~~and other values may cause the GPU to hang~~

+

| float1.5.10, Texture bias (upper 8 bits)

|}

−

This ~~sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this~~ register is ~~normally~~ used to ~~set~~ the ~~geometry shader entrypoint, it can also be used to set this single shader~~ unit ~~to run from a different entrypoint than the other three even when running a vertex shader~~.

+

This register is used to configure the procedural texture unit.

−

~~=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===~~

+

Minification filter values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-3

+

| 0

−

| ~~Index of geometry shader input register which the 1st attribute will be stored in.~~

+

| Nearest

|-

−

| ~~4-7~~

+

| 1

−

| ~~Index of geometry shader input register which the 2nd attribute will be stored in.~~

+

| Linear

|-

−

| ~~8-11~~

+

| 2

−

| ~~Index of geometry shader input register which the 3rd attribute will be stored in.~~

+

| Nearest, Mipmap Nearest

|-

−

| ~~12-15~~

+

| 3

−

| ~~Index of geometry shader input register which the 4th attribute will be stored in.~~

+

| Linear, Mipmap Nearest

|-

−

| ~~16-19~~

+

| 4

−

| ~~Index of geometry shader input register which the 5th attribute will be stored in.~~

+

| Nearest, Mipmap Linear

|-

−

| ~~20-23~~

+

| 5

−

| ~~Index of geometry shader input register which the 6th attribute will be stored in.~~

+

| Linear, Mipmap Linear

−

|-

−

~~| 24-27~~

−

~~| Index of geometry shader input register which the 7th attribute will be stored in.~~

−

|-

−

~~| 28-31~~

−

~~| Index of geometry shader input register which the 8th attribute will be stored in.~~

|}

−

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.

+

=== GPUREG_TEXUNIT3_PROCTEX5 ===

−

~~For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.~~

−

=== ~~GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH~~ ===

{| class="wikitable" border="1"

Line 4,773: Line 5,044:

! Description

|-

−

| 0-3

+

| 0-7

−

| ~~Index of geometry shader input register which the 9th attribute will be stored in.~~

+

| unsigned, Texture offset (Mipmap level 0 / base level)

|-

−

| 4-7

+

| 8-15

−

| ~~Index of geometry shader input register which the 10th attribute will be stored in.~~

+

| unsigned, mipmap level 1 offset (usually 0x80)

|-

−

| 8-11

+

| 16-23

−

| ~~Index of geometry shader input register which the 11th attribute will be stored in.~~

+

| unsigned, mipmap level 2 offset (usually 0xC0)

|-

−

| 12-15

+

| 24-31

−

| ~~Index of geometry shader input~~ register ~~which~~ the ~~12th attribute will~~ be ~~stored in~~.

+

| unsigned, mipmap level 3 offset (usually 0xE0)

+

|}

+

This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

+

=== GPUREG_PROCTEX_LUT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 16-19

+

| 0-7

−

| Index ~~of geometry shader input register which the 13th attribute will be stored in.~~

+

| unsigned, Index

|-

−

| 20-23

+

| 8-11

−

| ~~Index of geometry shader input register which the 14th attribute will be stored in.~~

+

| unsigned, Reference table

−

|-

−

~~| 24-27~~

−

~~| Index of geometry shader input register which the 15th attribute will be stored in.~~

−

|-

−

~~| 28-31~~

−

~~| Index of geometry shader input register which the 16th attribute will be stored in.~~

|}

−

This register ~~sets the geometry shader input register index which will correspond~~ to ~~each attribute contained by the input buffer (~~which ~~in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.~~

+

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

−

~~For example, having bits 0~~-~~3 set~~ to ~~5 means that~~, ~~in the geometry shader program~~, ~~v5 will contain the input buffer's 9th attribute~~.

−

~~=== GPUREG_GSH_OUTMAP_MASK ===~~

+

Reference table values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

| 0

−

| ~~Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)~~

+

| Noise table

−

|-

−

~~| 1~~

−

~~| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)~~

|-

| 2

−

| ~~Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)~~

+

| RGB mapping function table

|-

| 3

−

| ~~Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)~~

+

| Alpha mapping function table

|-

| 4

−

| ~~Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)~~

+

| Color table

|-

| 5

−

| ~~Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)~~

+

| Color difference table

−

|-

−

~~| 6~~

−

~~| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)~~

|}

−

~~This register toggles the geometry shader unit's output registers.~~

+

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

−

=== ~~GPUREG_GSH_CODETRANSFER_END~~ ===

{| class="wikitable" border="1"

Line 4,837: Line 5,102:

! Description

|-

−

| 0

+

| 0-31

−

| ~~Code~~ data ~~transfer end signal bit.~~

+

| LUT data

|}

−

~~This register's~~ value ~~should be set~~ to ~~1 in order to finalize~~ the ~~transfer of geometry shader code. It is unknown whether this register is used for other functions~~.

+

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

−

=== ~~GPUREG_GSH_FLOATUNIFORM_CONFIG~~ ===

+

==== Noise Table ====

+

128 elements:

{| class="wikitable" border="1"

! Bits

! Description

|-

−

| 0-6

+

| 0-11

−

| ~~Target float vec4 geometry shader uniform ID for transfer~~. ~~(range~~ 0~~-95~~, ~~where 0 = c0 and 95 = c95)~~

+

| fixed0.0.12, Value

|-

−

| 31

+

| 12-23

−

| ~~Float vec4 geometry shader uniform data transfer mode~~. (0 ~~= float24~~, 1 ~~= float32~~)

+

| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element

|}

−

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.

+

==== RGB Mapping Function Table ====

−

=== ~~GPUREG_GSH_FLOATUNIFORM_DATA~~ ===

+

128 elements:

{| class="wikitable" border="1"

! Bits

! Description

|-

−

| 0-31

+

| 0-11

−

| ~~Float vec4 geometry shader uniform data~~. ~~(format depends on transfer mode~~, ~~see below for details)~~

+

| fixed0.0.12, Value

+

|-

+

| 12-23

+

| fixed0.0.12 with two's complement, Difference from next element

|}

−

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].

+

==== Alpha Mapping Function Table ====

−

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :

−

** first word : ZZWWWWWW

−

** second word : YYYYZZZZ

−

** third word : XXXXXXYY

−

* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

−

=== ~~GPUREG_GSH_CODETRANSFER_CONFIG~~ ===

+

128 elements:

{| class="wikitable" border="1"

! Bits

Line 4,883: Line 5,144:

|-

| 0-11

−

| ~~Target geometry shader code offset for data transfer~~.

+

| fixed0.0.12, Value

+

|-

+

| 12-23

+

| fixed0.0.12 with two's complement, Difference from next element

|}

−

~~This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.~~

+

==== Color Table ====

−

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

−

=== ~~GPUREG_GSH_CODETRANSFER_DATA~~ ===

+

256 elements:

{| class="wikitable" border="1"

! Bits

! Description

|-

−

| 0-31

+

| 0-7

−

| ~~Geometry shader instruction data.~~

+

| unsigned, Red

+

|-

+

| 8-15

+

| unsigned, Green

+

|-

+

| 16-23

+

| unsigned, Blue

+

|-

+

| 24-31

+

| unsigned, Alpha

|}

−

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

+

==== Color Difference Table ====

−

=== ~~GPUREG_GSH_OPDESCS_CONFIG~~ ===

+

256 elements:

{| class="wikitable" border="1"

! Bits

! Description

|-

−

| 0-6

+

| 0-7

−

| ~~Target geometry shader operand descriptor offset for data transfer.~~

+

| signed, Half of red difference between current and next color table elements

+

|-

+

| 8-15

+

| signed, Half of green difference between current and next color table elements

+

|-

+

| 16-23

+

| signed, Half of blue difference between current and next color table elements

+

|-

+

| 24-31

+

| signed, Half of alpha difference between current and next color table elements

|}

−

~~This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.~~

+

=== GPUREG_TEXENV''i''_SOURCE ===

−

=== ~~GPUREG_GSH_OPDESCS_DATA~~ ===

{| class="wikitable" border="1"

Line 4,920: Line 5,196:

! Description

|-

−

| 0-31

+

| 0-3

−

| ~~Geometry shader operand descriptor data.~~

+

| unsigned, RGB source 0

+

|-

+

| 4-7

+

| unsigned, RGB source 1

+

|-

+

| 8-11

+

| unsigned, RGB source 2

+

|-

+

| 16-19

+

| unsigned, Alpha source 0

+

|-

+

| 20-23

+

| unsigned, Alpha source 1

+

|-

+

| 24-27

+

| unsigned, Alpha source 2

|}

−

This register ~~is used to transfer geometry shader operand descriptor data. This register behaves as~~ a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

+

This register configures a texture combiner's sources.

−

~~== Vertex shader registers ==~~

−

~~=== GPUREG_VSH_BOOLUNIFORM ===~~

+

Source values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

| 0

−

| ~~Value of vertex shader unit's b0 boolean register. (0=true, 1=false)~~

+

| Primary color

|-

| 1

−

| ~~Value of vertex shader unit's b1 boolean register. (0=true, 1=false)~~

+

| Fragment primary color

|-

| 2

−

| ~~Value of vertex shader unit's b2 boolean register. (0=true, 1=false)~~

+

| Fragment secondary color

|-

| 3

−

| ~~Value of vertex shader unit's b3 boolean register. (~~0~~=true, 1=false)~~

+

| Texture 0

|-

| 4

−

| ~~Value of vertex shader unit's b4 boolean register. (0=true,~~ 1~~=false)~~

+

| Texture 1

|-

| 5

−

| ~~Value of vertex shader unit's b5 boolean register. (0=true, 1=false)~~

+

| Texture 2

|-

| 6

−

| ~~Value of vertex shader unit's b6 boolean register. (0=true, 1=false)~~

+

| Texture 3

−

|-

−

~~| 7~~

−

~~| Value of vertex shader unit's b7 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 8~~

−

~~| Value of vertex shader unit's b8 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 9~~

−

~~| Value of vertex shader unit's b9 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 10~~

−

~~| Value of vertex shader unit's b10 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 11~~

−

~~| Value of vertex shader unit's b11 boolean register. (0=true, 1=false)~~

−

|-

−

~~| 12~~

−

~~| Value of vertex shader unit's b12 boolean register. (0=true, 1=false)~~

|-

| 13

−

| ~~Value of vertex shader unit's b13 boolean register. (0=true, 1=false)~~

+

| Previous buffer

|-

| 14

−

| ~~Value of vertex shader unit~~'~~s b14 boolean register. (0=true, 1=false~~)

+

| Constant (from GPUREG_TEXENV''i''_COLOR)

|-

| 15

−

| ~~Value of vertex shader unit's b15 boolean register. (0=true, 1=false)~~

+

| Previous

−

|-

−

~~| 16-31~~

−

~~| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang~~

|}

−

~~This register is used to set~~ the ~~vertex shader unit's boolean registers~~.

+

Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.

−

=== ~~GPUREG_VSH_INTUNIFORM_I0~~ ===

+

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"

Line 4,994: Line 5,262:

! Description

|-

−

| 0-7

+

| 0-3

−

| ~~Value for vertex shader's i0.x (u8~~, 0~~-255)~~

+

| unsigned, RGB operand 0

|-

−

| 8-15

+

| 4-7

−

| ~~Value for vertex shader's i0.y (u8~~, ~~0-255)~~

+

| unsigned, RGB operand 1

|-

−

| 16-23

+

| 8-11

−

| ~~Value for vertex shader's i0.z (u8~~, 0-~~255)~~

+

| unsigned, RGB operand 2

+

|-

+

| 12-14

+

| unsigned, Alpha operand 0

+

|-

+

| 16-18

+

| unsigned, Alpha operand 1

|-

−

| 24-31

+

| 20-22

−

| ~~Value for vertex shader's i0.w (u8~~, ~~0-255)~~

+

| unsigned, Alpha operand 2

|}

−

This register ~~is used to set the vertex shader~~'s ~~i0 integer register~~.

+

This register configures a texture combiner's operands.

−

~~=== GPUREG_VSH_INTUNIFORM_I1 ===~~

+

RGB operand values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-7

+

| 0

−

| ~~Value for vertex shader's i1.x (u8, 0~~-~~255)~~

+

| Source color

+

|-

+

| 1

+

| One minus source color

+

|-

+

| 2

+

| Source alpha

|-

−

| ~~8-15~~

+

| 3

−

| ~~Value for vertex shader's i1.y (u8, 0-255)~~

+

| One minus source alpha

|-

−

| ~~16-23~~

+

| 4

−

| ~~Value for vertex shader's i1.z (u8, 0-255)~~

+

| Source red

|-

−

| ~~24-31~~

+

| 5

−

| ~~Value for vertex shader's i1.w (u8, 0-255)~~

+

| One minus source red

−

|}

−

~~This register is used to set the vertex shader's i1 integer register.~~

−

~~=== GPUREG_VSH_INTUNIFORM_I2 ===~~

−

~~{| class="wikitable" border="1"~~

−

~~! Bits~~

−

~~! Description~~

|-

−

| ~~0-7~~

+

| 8

−

| ~~Value for vertex shader's i2.x (u8, 0-255)~~

+

| Source green

|-

−

| ~~8-15~~

+

| 9

−

| ~~Value for vertex shader's i2.y (u8, 0-255)~~

+

| One minus source green

|-

−

| ~~16-23~~

+

| 12

−

| ~~Value for vertex shader's i2.z (u8, 0-255)~~

+

| Source blue

|-

−

| ~~24-31~~

+

| 13

−

| ~~Value for vertex shader's i2.w (u8, 0-255)~~

+

| One minus source blue

|}

−

~~This register is used to set the vertex shader's i2 integer register.~~

+

Alpha operand values:

−

~~=== GPUREG_VSH_INTUNIFORM_I3 ===~~

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-7

+

| 0

−

| ~~Value for vertex shader's i3.x (u8, 0-255)~~

+

| Source alpha

|-

−

| ~~8-15~~

+

| 1

−

| ~~Value for vertex shader's i3.y (u8, 0-255)~~

+

| One minus source alpha

|-

−

| ~~16-23~~

+

| 2

−

| ~~Value for vertex shader's i3.z (u8, 0-255)~~

+

| Source red

|-

−

| ~~24-31~~

+

| 3

−

| ~~Value for vertex shader's i3.w (u8, 0~~-~~255)~~

+

| One minus source red

−

|}

+

|-

−

+

| 4

−

~~This register is used to set the vertex shader's i3 integer register.~~

+

| Source green

−

~~=== GPUREG_VSH_INPUTBUFFER_CONFIG ===~~

−

{| ~~class="wikitable" border="1"~~

−

~~! Bits~~

−

~~! Description~~

|-

−

| ~~0-7~~

+

| 5

−

| ~~Input buffer stride~~ minus ~~1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)~~

+

| One minus source green

|-

−

| ~~8-23~~

+

| 6

−

| ~~Unknown. These bits typically aren't updated by games.~~

+

| Source blue

|-

−

| ~~24-31~~

+

| 7

−

| ~~Unknown. This is typically set to 0xA for vertex shaders.~~

+

| One minus source blue

|}

−

~~This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.~~

+

=== GPUREG_TEXENV''i''_COMBINER ===

−

=== ~~GPUREG_VSH_ENTRYPOINT~~ ===

{| class="wikitable" border="1"

Line 5,096: Line 5,357:

! Description

|-

−

| 0-15

+

| 0-3

−

| ~~Vertex shader entrypoint~~, ~~in words.~~

+

| unsigned, RGB combine

|-

−

| 16-31

+

| 16-19

−

| ~~Unknown. This seems to always be set to 0x7FFF~~, ~~and other values may cause the GPU to hang~~

+

| unsigned, Alpha combine

|}

−

This ~~sets the entrypoint for the program running on shader units set to vertex shader~~ mode~~. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them~~.

+

This register configures a texture combiner's combine mode.

−

~~=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===~~

+

Combine values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

−

| 0-3

+

| 0

−

| ~~Index of vertex shader input register which the 1st attribute will be stored in.~~

+

| Replace

+

|-

+

| 1

+

| Modulate

+

|-

+

| 2

+

| Add

|-

−

| ~~4-7~~

+

| 3

−

| ~~Index of vertex shader input register which the 2nd attribute will be stored in.~~

+

| Add signed

|-

−

| ~~8-11~~

+

| 4

−

| ~~Index of vertex shader input register which the 3rd attribute will be stored in.~~

+

| Interpolate

|-

−

| ~~12-15~~

+

| 5

−

| ~~Index of vertex shader input register which the 4th attribute will be stored in.~~

+

| Subtract

|-

−

| ~~16-19~~

+

| 6

−

| ~~Index of vertex shader input register which the 5th attribute will be stored in.~~

+

| Dot3 RGB

|-

−

| ~~20-23~~

+

| 7

−

| ~~Index of vertex shader input register which the 6th attribute will be stored in.~~

+

| Dot3 RGBA

|-

−

| ~~24-27~~

+

| 8

−

| ~~Index of vertex shader input register which the 7th attribute will be stored in.~~

+

| Multiply then add

|-

−

| ~~28-31~~

+

| 9

−

| ~~Index of vertex shader input register which the 8th attribute will be stored in.~~

+

| Add then multiply

|}

−

~~This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.~~

+

=== GPUREG_TEXENV''i''_COLOR ===

−

~~For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.~~

−

=== ~~GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH~~ ===

{| class="wikitable" border="1"

Line 5,145: Line 5,409:

! Description

|-

−

| 0-3

+

| 0-7

−

| ~~Index of vertex shader input register which the 9th attribute will be stored in.~~

+

| unsigned, Red

|-

−

| 4-7

+

| 8-15

−

| ~~Index of vertex shader input register which the 10th attribute will be stored in.~~

+

| unsigned, Green

|-

−

| 8-11

+

| 16-23

−

| ~~Index of vertex shader input register which the 11th attribute will be stored in.~~

+

| unsigned, Blue

|-

−

| 12-15

+

| 24-31

−

| ~~Index of vertex shader input register which the 12th attribute will be stored in.~~

+

| unsigned, Alpha

−

|-

+

|}

−

~~| 16-19~~

+

−

~~| Index of vertex shader input~~ register ~~which the 13th attribute will be stored in~~.

+

This register configures a texture combiner's constant color.

−

|-

+

−

~~| 20-23~~

+

=== GPUREG_TEXENV''i''_SCALE ===

−

~~| Index of vertex shader input register which the 14th attribute will be stored in.~~

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

|-

−

| 24-27

+

| 0-1

−

| ~~Index of vertex shader input register which the 15th attribute will be stored in.~~

+

| unsigned, RGB scale

|-

−

| 28-31

+

| 16-17

−

| ~~Index of vertex shader input register which the 16th attribute will be stored in.~~

+

| unsigned, Alpha scale

|}

−

This register ~~sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.~~

+

This register configures a texture combiner's scale value.

−

~~For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer~~'s ~~9th attribute~~.

−

~~=== GPUREG_VSH_OUTMAP_MASK ===~~

+

Scale values:

{| class="wikitable" border="1"

−

! ~~Bits~~

+

! Value

! Description

|-

| 0

−

| ~~Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)~~

+

| 1x

|-

| 1

−

| ~~Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)~~

+

| 2x

|-

| 2

−

| ~~Enable bit for vertex shader's o2 output register. (~~1 ~~= o2 enabled~~, ~~0 = o2 disabled)~~

+

| 4x

+

|}

+

=== GPUREG_TEXENV_UPDATE_BUFFER ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, Fog mode

|-

| 3

−

| ~~Enable bit for vertex shader's o3 output register. (1 = o3 enabled~~, ~~0 = o3 disabled)~~

+

| unsigned, Shading density source

−

|-

−

~~| 4~~

−

~~| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)~~

−

|-

−

~~| 5~~

−

~~| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)~~

−

|-

−

~~| 6~~

−

~~| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)~~

−

|-

−

~~| 7~~

−

~~| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)~~

|-

| 8

−

| ~~Enable bit for vertex shader's o8 output register. (~~1 ~~= o8 enabled, 0 = o8 disabled)~~

+

| unsigned, TexEnv 1 RGB buffer input

|-

| 9

−

| ~~Enable bit for vertex shader's o9 output register. (1 = o9 enabled~~, ~~0 = o9 disabled)~~

+

| unsigned, TexEnv 2 RGB buffer input

|-

| 10

−

| ~~Enable bit for vertex shader's o10 output register. (1 = o10 enabled~~, ~~0 = o10 disabled)~~

+

| unsigned, TexEnv 3 RGB buffer input

|-

| 11

−

| ~~Enable bit for vertex shader's o11 output register. (1 = o11 enabled~~, ~~0 = o11 disabled)~~

+

| unsigned, TexEnv 4 RGB buffer input

|-

| 12

−

| ~~Enable bit for vertex shader's o12 output register. (~~1 ~~= o12 enabled, 0 = o12 disabled)~~

+

| unsigned, TexEnv 1 alpha buffer input

|-

| 13

−

| ~~Enable bit for vertex shader's o13 output register. (1 = o13 enabled~~, ~~0 = o13 disabled)~~

+

| unsigned, TexEnv 2 alpha buffer input

−

|-

+

|-

−

| 14

+

| 14

−

| ~~Enable bit for vertex shader's o14 output register. (1 = o14 enabled~~, ~~0 = o14 disabled)~~

+

| unsigned, TexEnv 3 alpha buffer input

−

|-

+

|-

−

| 15

+

| 15

−

| ~~Enable bit for vertex shader's o15 output register.~~ (1 = ~~o15 enabled~~, 0 = ~~o15 disabled~~)

+

| unsigned, TexEnv 4 alpha buffer input

−

|}

+

|-

−

+

| 16

−

This register ~~toggles~~ the ~~vertex shader units' output registers~~.

+

| unsigned, Z flip (0 = don't flip, 1 = flip)

−

+

|-

−

~~=== GPUREG_VSH_CODETRANSFER_END ===~~

+

| 24-25

−

+

| 0x0

−

{| class="wikitable" border="1"

+

|}

−

! ~~Bits~~

+

−

! Description

+

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

−

|-

+

−

| 0

+

Fog mode values:

−

| ~~Code data transfer end signal bit.~~

+

−

|}

+

{| class="wikitable" border="1"

−

+

! Value

−

~~This register's value should be set to~~ 1 ~~in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.~~

+

! Description

−

+

|-

−

~~=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===~~

+

| 0

−

+

| Disabled

−

~~{| class="wikitable" border="1"~~

+

|-

−

! ~~Bits~~

+

| 5

−

! Description

+

| Fog

−

|-

+

|-

−

| 0-6

+

| 7

−

| ~~Target float vec4 vertex shader uniform ID for transfer. (range 0~~-~~95, where 0 = c0 and 95 = c95)~~

+

| Gas

−

|-

+

|}

−

| 31

+

−

| ~~Float vec4 vertex shader uniform data transfer mode. (0~~ = ~~float24,~~ 1 = ~~float32~~)

+

Shading density source values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Plain density

+

|-

+

| 1

+

| Depth density

+

|}

+

Buffer input values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Previous buffer

+

|-

+

| 1

+

| Previous

+

|}

+

=== GPUREG_FOG_COLOR ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Red

+

|-

+

| 8-15

+

| unsigned, Green

+

|-

+

| 16-23

+

| unsigned, Blue

+

|}

+

This register is used to configure the color of fog.

+

=== GPUREG_GAS_ATTENUATION ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| float1.5.10, Gas density attenuation

+

|}

+

This register is used to configure the gas density attenuation.

+

=== GPUREG_GAS_ACCMAX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| float1.5.10, Gas maximum density accumulation

+

|}

+

This register is used to configure the gas maximum density accumulation.

+

=== GPUREG_FOG_LUT_INDEX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| unsigned, Index

+

|}

+

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

+

=== GPUREG_FOG_LUT_DATA''i'' ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-23

+

| LUT data

+

|}

+

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

+

==== Fog Look-Up Table ====

+

128 elements:

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-12

+

| fixed1.1.11, Difference from next element

+

|-

+

| 13-23

+

| fixed0.0.11, Value

+

|}

+

=== GPUREG_TEXENV_BUFFER_COLOR ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Red

+

|-

+

| 8-15

+

| unsigned, Green

+

|-

+

| 16-23

+

| unsigned, Blue

+

|-

+

| 24-31

+

| unsigned, Alpha

+

|}

+

This register is used to configure the texture combiner buffer color.

+

== Framebuffer registers ==

+

=== GPUREG_COLOR_OPERATION ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-1

+

| unsigned, Fragment operation mode

+

|-

+

| 8

+

| unsigned, Blend mode

+

|-

+

| 16-25

+

| 0x0E4

+

|}

+

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

+

Fragment operation mode values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Default

+

|-

+

| 1

+

| Gas

+

|-

+

| 3

+

| Shadow

+

|}

+

Blend mode values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Logic op

+

|-

+

| 1

+

| Blend

+

|}

+

=== GPUREG_BLEND_FUNC ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, RGB equation

+

|-

+

| 8-10

+

| unsigned, Alpha equation

+

|-

+

| 16-19

+

| unsigned, RGB source function

+

|-

+

| 20-23

+

| unsigned, RGB destination function

+

|-

+

| 24-27

+

| unsigned, Alpha source function

+

|-

+

| 28-31

+

| unsigned, Alpha destination function

+

|}

+

This register is used to configure the blending function.

+

'''Equation values:'''

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Add

+

|-

+

| 1

+

| Subtract

+

|-

+

| 2

+

| Reverse subtract

+

|-

+

| 3

+

| Minimum

+

|-

+

| 4

+

| Maximum

+

|}

+

Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)

+

'''Function values:'''

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Zero

+

|-

+

| 1

+

| One

+

|-

+

| 2

+

| Source color

+

|-

+

| 3

+

| One minus source color

+

|-

+

| 4

+

| Destination color

+

|-

+

| 5

+

| One minus destination color

+

|-

+

| 6

+

| Source alpha

+

|-

+

| 7

+

| One minus source alpha

+

|-

+

| 8

+

| Destination alpha

+

|-

+

| 9

+

| One minus destination alpha

+

|-

+

| 10

+

| Constant color

+

|-

+

| 11

+

| One minus constant color

+

|-

+

| 12

+

| Constant alpha

+

|-

+

| 13

+

| One minus constant alpha

+

|-

+

| 14

+

| Source alpha saturate

+

|}

+

=== GPUREG_LOGIC_OP ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Logic op

+

|}

+

This register is used to configure the logic op.

+

Logic op values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Clear

+

|-

+

| 1

+

| AND

+

|-

+

| 2

+

| Reverse AND

+

|-

+

| 3

+

| Copy

+

|-

+

| 4

+

| Set

+

|-

+

| 5

+

| Inverted copy

+

|-

+

| 6

+

| Noop

+

|-

+

| 7

+

| Invert

+

|-

+

| 8

+

| NAND

+

|-

+

| 9

+

| OR

+

|-

+

| 10

+

| NOR

+

|-

+

| 11

+

| XOR

+

|-

+

| 12

+

| Equivalent

+

|-

+

| 13

+

| Inverted AND

+

|-

+

| 14

+

| Reverse OR

+

|-

+

| 15

+

| Inverted OR

+

|}

+

=== GPUREG_BLEND_COLOR ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Red

+

|-

+

| 8-15

+

| unsigned, Green

+

|-

+

| 16-23

+

| unsigned, Blue

+

|-

+

| 24-31

+

| unsigned, Alpha

+

|}

+

This register is used to configure the blending color.

+

=== GPUREG_FRAGOP_ALPHA_TEST ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

+

|-

+

| 4-6

+

| unsigned, Function

+

|-

+

| 8-15

+

| unsigned, Reference value

+

|}

+

This register is used to configure alpha testing.

+

Function values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Never

+

|-

+

| 1

+

| Always

+

|-

+

| 2

+

| Equal

+

|-

+

| 3

+

| Not equal

+

|-

+

| 4

+

| Less than

+

|-

+

| 5

+

| Less than or equal

+

|-

+

| 6

+

| Greater than

+

|-

+

| 7

+

| Greater than or equal

+

|}

+

=== GPUREG_STENCIL_TEST ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

+

|-

+

| 4-6

+

| unsigned, Function

+

|-

+

| 8-15

+

| unsigned, Buffer mask

+

|-

+

| 16-23

+

| signed, Reference value

+

|-

+

| 24-31

+

| unsigned, Mask

+

|}

+

This register is used to configure stencil testing.

+

Function values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Never

+

|-

+

| 1

+

| Always

+

|-

+

| 2

+

| Equal

+

|-

+

| 3

+

| Not equal

+

|-

+

| 4

+

| Less than

+

|-

+

| 5

+

| Less than or equal

+

|-

+

| 6

+

| Greater than

+

|-

+

| 7

+

| Greater than or equal

+

|}

+

=== GPUREG_STENCIL_OP ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, Fail operation

+

|-

+

| 4-6

+

| unsigned, Z-fail operation

+

|-

+

| 8-10

+

| unsigned, Z-pass operation

+

|}

+

This register is used to configure stencil result operations.

+

Operation values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Keep

+

|-

+

| 1

+

| Zero

+

|-

+

| 2

+

| Replace

+

|-

+

| 3

+

| Increment

+

|-

+

| 4

+

| Decrement

+

|-

+

| 5

+

| Invert

+

|-

+

| 6

+

| Increment and wrap

+

|-

+

| 7

+

| Decrement and wrap

+

|}

+

=== GPUREG_DEPTH_COLOR_MASK ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Depth test enabled (0 = disabled, 1 = enabled)

+

|-

+

| 4-6

+

| unsigned, Depth function

+

|-

+

| 8

+

| unsigned, Red write enabled (0 = disabled, 1 = enabled)

+

|-

+

| 9

+

| unsigned, Green write enabled (0 = disabled, 1 = enabled)

+

|-

+

| 10

+

| unsigned, Blue write enabled (0 = disabled, 1 = enabled)

+

|-

+

| 11

+

| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)

+

|-

+

| 12

+

| unsigned, Depth write enabled (0 = disabled, 1 = enabled)

+

|}

+

This register is used to depth testing and framebuffer write masking.

+

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

+

Depth function values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Never

+

|-

+

| 1

+

| Always

+

|-

+

| 2

+

| Equal

+

|-

+

| 3

+

| Not equal

+

|-

+

| 4

+

| Less than

+

|-

+

| 5

+

| Less than or equal

+

|-

+

| 6

+

| Greater than

+

|-

+

| 7

+

| Greater than or equal

+

|}

+

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Trigger (0 = idle, 1 = invalidate)

+

|-

+

| 1-31

+

| 0x0

+

|}

+

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

+

=== GPUREG_FRAMEBUFFER_FLUSH ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Trigger (0 = idle, 1 = flush)

+

|-

+

| 1-31

+

| 0x0

+

|}

+

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

+

=== GPUREG_COLORBUFFER_READ ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Allow read (0 = disable, 0xF = enable)

+

|}

+

This register configures read access from the color buffer.

+

=== GPUREG_COLORBUFFER_WRITE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Allow write (0 = disable, 0xF = enable)

+

|}

+

This register configures write access to the color buffer.

+

=== GPUREG_DEPTHBUFFER_READ ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Allow stencil read (0 = disable, 1 = enable)

+

|-

+

| 1

+

| unsigned, Allow depth read (0 = disable, 1 = enable)

+

|}

+

This register configures read access from the depth and stencil buffers.

+

=== GPUREG_DEPTHBUFFER_WRITE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Allow stencil write (0 = disable, 1 = enable)

+

|-

+

| 1

+

| unsigned, Allow depth write (0 = disable, 1 = enable)

+

|}

+

This register configures write access to the depth and stencil buffers.

+

=== GPUREG_DEPTHBUFFER_FORMAT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-1

+

| unsigned, Format

+

|}

+

This register configures the depth buffer data format.

+

Format values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| 16-bit depth

+

|-

+

| 2

+

| 24-bit depth

+

|-

+

| 3

+

| 24-bit depth + 8-bit stencil

+

|}

+

=== GPUREG_COLORBUFFER_FORMAT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-1

+

| unsigned, Pixel size

+

|-

+

| 16-18

+

| unsigned, Format

+

|}

+

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

+

Pixel size values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| 16-bit color

+

|-

+

| 2

+

| 32-bit color

+

|}

+

Format values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| RGBA8/Gas

+

|-

+

| 2

+

| RGB5A1

+

|-

+

| 3

+

| RGB565

+

|-

+

| 4

+

| RGBA4

+

|}

+

=== GPUREG_EARLYDEPTH_TEST2 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Enabled (0 = disabled, 1 = enabled)

+

|}

+

This register enables the early depth test.

+

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Render block mode

+

|}

+

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

+

Render block mode values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| 8x8 blocks

+

|-

+

| 1

+

| 32x32 blocks

+

|}

+

=== GPUREG_DEPTHBUFFER_LOC ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-27

+

| unsigned, Depth buffer physical address >> 3

+

|}

+

This register configures the depth buffer physical address.

+

=== GPUREG_COLORBUFFER_LOC ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-27

+

| unsigned, Color buffer physical address >> 3

+

|}

+

This register configures the color buffer physical address.

+

=== GPUREG_FRAMEBUFFER_DIM ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-10

+

| unsigned, Width

+

|-

+

| 12-21

+

| unsigned, Height - 1

+

|-

+

| 24

+

| 0x1

+

|}

+

This register configures the framebuffer dimensions.

+

=== GPUREG_GAS_LIGHT_XY ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Planar shading minimum intensity

+

|-

+

| 8-15

+

| unsigned, Planar shading maximum intensity

+

|-

+

| 16-23

+

| unsigned, Planar shading density attenuation

+

|}

+

This register configures gas light planar shading.

+

=== GPUREG_GAS_LIGHT_Z ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, View shading minimum intensity

+

|-

+

| 8-15

+

| unsigned, View shading maximum intensity

+

|-

+

| 16-23

+

| unsigned, View shading density attenuation

+

|}

+

This register configures gas light view shading.

+

=== GPUREG_GAS_LIGHT_Z_COLOR ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, View shading effect in line-of-sight direction

+

|-

+

| 8

+

| Gas color LUT input

+

|}

+

This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.

+

Color LUT input values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Gas density

+

|-

+

| 1

+

| Light factor

+

|}

+

=== GPUREG_GAS_LUT_INDEX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| unsigned, Index

+

|}

+

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

+

=== GPUREG_GAS_LUT_DATA ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| LUT data

+

|}

+

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

+

==== Gas Look-Up Table ====

+

16 elements:

+

First 8 elements:

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| signed, Red

+

|-

+

| 8-15

+

| signed, Green

+

|-

+

| 16-23

+

| signed, Blue

+

|}

+

Last 8 elements:

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Red

+

|-

+

| 8-15

+

| unsigned, Green

+

|-

+

| 16-23

+

| unsigned, Blue

+

|}

+

=== GPUREG_GAS_DELTAZ_DEPTH ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-23

+

| fixed0.16.8, Depth direction attenuation proportion

+

|-

+

| 24-25

+

| unsigned, Depth function

+

|}

+

This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.

+

Gas depth function values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Never

+

|-

+

| 1

+

| Always

+

|-

+

| 2

+

| Greater than/Greater than or equal

+

|-

+

| 3

+

| Less than/Less than or equal/Equal/Not equal

+

|}

+

=== GPUREG_FRAGOP_SHADOW ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| float1.5.10, Sum of penumbra scale and penumbra bias

+

|-

+

| 16-31

+

| float1.5.10, Penumbra scale with reversed sign

+

|}

+

This register is used to configure shadow properties.

+

== Fragment lighting registers ==

+

=== GPUREG_LIGHT''i''_SPECULAR0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Blue

+

|-

+

| 10-17

+

| unsigned, Green

+

|-

+

| 20-27

+

| unsigned, Red

+

|}

+

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

+

=== GPUREG_LIGHT''i''_SPECULAR1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Blue

+

|-

+

| 10-17

+

| unsigned, Green

+

|-

+

| 20-27

+

| unsigned, Red

+

|}

+

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

+

=== GPUREG_LIGHT''i''_DIFFUSE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Blue

+

|-

+

| 10-17

+

| unsigned, Green

+

|-

+

| 20-27

+

| unsigned, Red

+

|}

+

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

+

=== GPUREG_LIGHT''i''_AMBIENT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Blue

+

|-

+

| 10-17

+

| unsigned, Green

+

|-

+

| 20-27

+

| unsigned, Red

+

|}

+

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

+

=== GPUREG_LIGHT''i''_XY ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| float1.5.10, X coordinate

+

|-

+

| 16-31

+

| float1.5.10, Y coordinate

+

|}

+

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

+

=== GPUREG_LIGHT''i''_Z ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| float1.5.10, Z coordinate

+

|}

+

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

+

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-12

+

| fixed1.1.11, X coordinate (negated)

+

|-

+

| 16-28

+

| fixed1.1.11, Y coordinate (negated)

+

|}

+

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

+

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-12

+

| fixed1.1.11, Z coordinate (negated)

+

|}

+

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

+

=== GPUREG_LIGHT''i''_CONFIG ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Light type (0 = positional light, 1 = directional light)

+

|-

+

| 1

+

| unsigned, Two side diffuse (0 = one side, 1 = both sides)

+

|-

+

| 2

+

| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)

+

|-

+

| 3

+

| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)

+

|}

+

This register configures a light's properties.

+

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-19

+

| float1.7.12, Distance attenuation bias

+

|}

+

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

+

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-19

+

| float1.7.12, Distance attenuation scale

+

|}

+

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

+

=== GPUREG_LIGHTING_AMBIENT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Blue

+

|-

+

| 10-17

+

| unsigned, Green

+

|-

+

| 20-27

+

| unsigned, Red

+

|}

+

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

+

=== GPUREG_LIGHTING_NUM_LIGHTS ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, Number of active lights - 1

+

|}

+

This register configures the number of active lights.

+

=== GPUREG_LIGHTING_CONFIG0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)

+

|-

+

| 2-3

+

| unsigned, Fresnel selector

+

|-

+

| 4-7

+

| unsigned, Light environment configuration

+

|-

+

| 8-11

+

| 0x4

+

|-

+

| 16

+

| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)

+

|-

+

| 17

+

| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)

+

|-

+

| 18

+

| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)

+

|-

+

| 19

+

| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)

+

|-

+

| 22-23

+

| unsigned, Bump map texture unit

+

|-

+

| 24-25

+

| unsigned, Shadow map texture unit

+

|-

+

| 27

+

| unsigned, Clamp highlights (0 = disabled, 1 = enabled)

+

|-

+

| 28-29

+

| unsigned, Bump mode

+

|-

+

| 30

+

| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)

+

|-

+

| 31

+

| 0x1

+

|}

+

This register configures the light environment.

+

Fresnel selector values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| None

+

|-

+

| 1

+

| Primary alpha

+

|-

+

| 2

+

| Secondary alpha

+

|-

+

| 3

+

| Primary and secondary alpha

+

|}

+

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

+

Light environment configuration values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

! Available LUTs

+

|-

+

| 0

+

| Configuration 0

+

| D0, RR, SP, DA

+

|-

+

| 1

+

| Configuration 1

+

| FR, RR, SP, DA

+

|-

+

| 2

+

| Configuration 2

+

| D0, D1, RR, DA

+

|-

+

| 3

+

| Configuration 3

+

| D0, D1, FR, DA

+

|-

+

| 4

+

| Configuration 4

+

| All except for FR

+

|-

+

| 5

+

| Configuration 5

+

| All except for D1

+

|-

+

| 6

+

| Configuration 6

+

| All except for RB and RG

+

|-

+

| 8

+

| Configuration 7

+

| All

+

|}

+

Bump mode values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Not used

+

|-

+

| 1

+

| Use as bump map

+

|-

+

| 2

+

| Use as tangent map

+

|}

+

=== GPUREG_LIGHTING_CONFIG1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 1

+

| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 2

+

| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 3

+

| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 4

+

| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 5

+

| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 6

+

| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 7

+

| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)

+

|-

+

| 8

+

| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 9

+

| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 10

+

| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 11

+

| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 12

+

| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 13

+

| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 14

+

| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 15

+

| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)

+

|-

+

| 16

+

| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)

+

|-

+

| 17

+

| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)

+

|-

+

| 18

+

| 0x1

+

|-

+

| 19

+

| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)

+

|-

+

| 20

+

| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)

+

|-

+

| 21

+

| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)

+

|-

+

| 22

+

| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)

+

|-

+

| 24

+

| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 25

+

| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 26

+

| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 27

+

| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 28

+

| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 29

+

| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 30

+

| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|-

+

| 31

+

| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)

+

|}

+

This register is used to disable various aspects of the light environment.

+

=== GPUREG_LIGHTING_LUT_INDEX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Starting index

+

|-

+

| 8-12

+

| unsigned, Look-up table

+

|}

+

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

+

Lookup table values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| D0

+

|-

+

| 1

+

| D1

+

|-

+

| 3

+

| FR

+

|-

+

| 4

+

| RB

+

|-

+

| 5

+

| RG

+

|-

+

| 6

+

| RR

+

|-

+

| 8-15

+

| SP0-7

+

|-

+

| 16-23

+

| DA0-7

+

|}

+

=== GPUREG_LIGHTING_ENABLE1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Disabled (0 = enabled, 1 = disabled)

+

|}

+

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

+

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-23

+

| LUT data

+

|}

+

Lighting LUT data is written here.

+

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

+

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

+

Format of an entry:

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-11

+

| fixed0.0.12, Entry value

+

|-

+

| 12-23

+

| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation

+

|}

+

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 1

+

| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)

+

|-

+

| 5

+

| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)

+

|-

+

| 9

+

| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)

+

|-

+

| 13

+

| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)

+

|-

+

| 17

+

| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)

+

|-

+

| 21

+

| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)

+

|-

+

| 25

+

| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)

+

|}

+

This register controls whether the absolute value of the input is taken before using a LUT.

+

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, Input selector for D0

+

|-

+

| 4-6

+

| unsigned, Input selector for D1

+

|-

+

| 8-10

+

| unsigned, Input selector for SP

+

|-

+

| 12-14

+

| unsigned, Input selector for FR

+

|-

+

| 16-18

+

| unsigned, Input selector for RB

+

|-

+

| 20-22

+

| unsigned, Input selector for RG

+

|-

+

| 24-26

+

| unsigned, Input selector for RR

+

|}

+

This register selects the input from LUTs.

+

Input selector values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| N·H

+

|-

+

| 1

+

| V·H

+

|-

+

| 2

+

| N·V

+

|-

+

| 3

+

| L·N

+

|-

+

| 4

+

| -L·P (aka Spotlight aka SP)

+

|-

+

| 5

+

| cos φ (aka CP)

+

|}

+

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, Scaler selector for D0

+

|-

+

| 4-6

+

| unsigned, Scaler selector for D1

+

|-

+

| 8-10

+

| unsigned, Scaler selector for SP

+

|-

+

| 12-14

+

| unsigned, Scaler selector for FR

+

|-

+

| 16-18

+

| unsigned, Scaler selector for RB

+

|-

+

| 20-22

+

| unsigned, Scaler selector for RG

+

|-

+

| 24-26

+

| unsigned, Scaler selector for RR

+

|}

+

This register controls the scaling that is applied to the output of a LUT.

+

Scaler selector values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| 1x

+

|-

+

| 1

+

| 2x

+

|-

+

| 2

+

| 4x

+

|-

+

| 3

+

| 8x

+

|-

+

| 6

+

| 0.25x

+

|-

+

| 7

+

| 0.5x

+

|}

+

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-2

+

| unsigned, ID of the 1st enabled light

+

|-

+

| 4-6

+

| unsigned, ID of the 2nd enabled light

+

|-

+

| 8-10

+

| unsigned, ID of the 3rd enabled light

+

|-

+

| 12-14

+

| unsigned, ID of the 4th enabled light

+

|-

+

| 16-18

+

| unsigned, ID of the 5th enabled light

+

|-

+

| 20-22

+

| unsigned, ID of the 6th enabled light

+

|-

+

| 24-26

+

| unsigned, ID of the 7th enabled light

+

|-

+

| 28-30

+

| unsigned, ID of the 8th enabled light

+

|}

+

This register sets the IDs of enabled light sources.

+

== Geometry pipeline registers ==

+

=== GPUREG_ATTRIBBUFFERS_LOC ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 1-28

+

| unsigned, Vertex arrays base address

+

|}

+

This register sets the base address of all vertex arrays.

+

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-1

+

| unsigned, Vertex attribute 0 type

+

|-

+

| 2-3

+

| unsigned, Vertex attribute 0 size

+

|-

+

| 4-5

+

| unsigned, Vertex attribute 1 type

+

|-

+

| 6-7

+

| unsigned, Vertex attribute 1 size

+

|-

+

| 8-9

+

| unsigned, Vertex attribute 2 type

+

|-

+

| 10-11

+

| unsigned, Vertex attribute 2 size

+

|-

+

| 12-13

+

| unsigned, Vertex attribute 3 type

+

|-

+

| 14-15

+

| unsigned, Vertex attribute 3 size

+

|-

+

| 16-17

+

| unsigned, Vertex attribute 4 type

+

|-

+

| 18-19

+

| unsigned, Vertex attribute 4 size

+

|-

+

| 20-21

+

| unsigned, Vertex attribute 5 type

+

|-

+

| 22-23

+

| unsigned, Vertex attribute 5 size

+

|-

+

| 24-25

+

| unsigned, Vertex attribute 6 type

+

|-

+

| 26-27

+

| unsigned, Vertex attribute 6 size

+

|-

+

| 28-29

+

| unsigned, Vertex attribute 7 type

+

|-

+

| 30-31

+

| unsigned, Vertex attribute 7 size

+

|}

+

This register configures the types and sizes of the first 8 vertex attributes.

+

Vertex attribute type values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Byte

+

|-

+

| 1

+

| Unsigned byte

+

|-

+

| 2

+

| Short

+

|-

+

| 3

+

| Float

+

|}

+

Vertex attribute size values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| 8 bits

+

|-

+

| 1

+

| 16 bits

+

|-

+

| 2

+

| 24 bits

+

|-

+

| 3

+

| 32 bits

+

|}

+

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-1

+

| unsigned, Vertex attribute 8 type

+

|-

+

| 2-3

+

| unsigned, Vertex attribute 8 size

+

|-

+

| 4-5

+

| unsigned, Vertex attribute 9 type

+

|-

+

| 6-7

+

| unsigned, Vertex attribute 9 size

+

|-

+

| 8-9

+

| unsigned, Vertex attribute 10 type

+

|-

+

| 10-11

+

| unsigned, Vertex attribute 10 size

+

|-

+

| 12-13

+

| unsigned, Vertex attribute 11 type

+

|-

+

| 14-15

+

| unsigned, Vertex attribute 11 size

+

|-

+

| 16-27

+

| unsigned, Fixed vertex attribute mask

+

|-

+

| 28-31

+

| unsigned, Total vertex attribute count - 1

+

|}

+

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

+

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

+

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-27

+

| unsigned, Offset from base vertex arrays address

+

|}

+

This register configures the offset of a vertex array from the base vertex arrays address.

+

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Component 1

+

|-

+

| 4-7

+

| unsigned, Component 2

+

|-

+

| 8-11

+

| unsigned, Component 3

+

|-

+

| 12-15

+

| unsigned, Component 4

+

|-

+

| 16-19

+

| unsigned, Component 5

+

|-

+

| 20-23

+

| unsigned, Component 6

+

|-

+

| 24-27

+

| unsigned, Component 7

+

|-

+

| 28-31

+

| unsigned, Component 8

+

|}

+

This register configures the first 8 component types of a vertex array.

+

Component values:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Vertex attribute 0

+

|-

+

| 1

+

| Vertex attribute 1

+

|-

+

| 2

+

| Vertex attribute 2

+

|-

+

| 3

+

| Vertex attribute 3

+

|-

+

| 4

+

| Vertex attribute 4

+

|-

+

| 5

+

| Vertex attribute 5

+

|-

+

| 6

+

| Vertex attribute 6

+

|-

+

| 7

+

| Vertex attribute 7

+

|-

+

| 8

+

| Vertex attribute 8

+

|-

+

| 9

+

| Vertex attribute 9

+

|-

+

| 10

+

| Vertex attribute 10

+

|-

+

| 11

+

| Vertex attribute 11

+

|-

+

| 12

+

| 4-byte padding

+

|-

+

| 13

+

| 8-byte padding

+

|-

+

| 14

+

| 12-byte padding

+

|-

+

| 15

+

| 16-byte padding

+

|}

+

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Component 9

+

|-

+

| 4-7

+

| unsigned, Component 10

+

|-

+

| 8-11

+

| unsigned, Component 11

+

|-

+

| 12-15

+

| unsigned, Component 12

+

|-

+

| 16-23

+

| unsigned, Bytes per vertex

+

|-

+

| 28-31

+

| unsigned, Total number of components

+

|}

+

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

+

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

+

=== GPUREG_INDEXBUFFER_CONFIG ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-27

+

| unsigned, Offset from base vertex arrays address

+

|-

+

| 31

+

| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)

+

|}

+

This register configures the index array used when drawing elements.

+

=== GPUREG_NUMVERTICES ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Number of vertices to render

+

|}

+

This register sets the number of vertices to render.

+

=== GPUREG_GEOSTAGE_CONFIG ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-1

+

| unsigned, Geometry shader in use (0 = not in use, 2 = in use)

+

|-

+

| 8

+

| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)

+

|-

+

| 9

+

| 0x0

+

|-

+

| 31

+

| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)

+

|}

+

This register configures the geometry stage of the GPU pipeline.

+

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

+

=== GPUREG_VERTEX_OFFSET ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Starting vertex offset

+

|}

+

This register sets the offset of the first vertex in an array to render.

+

=== GPUREG_POST_VERTEX_CACHE_NUM ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)

+

|}

+

This register configures the post-vertex cache.

+

=== GPUREG_DRAWARRAYS ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Trigger (0 = idle, non-zero = draw arrays)

+

|}

+

This register triggers drawing vertex arrays.

+

=== GPUREG_DRAWELEMENTS ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Trigger (0 = idle, non-zero = draw elements)

+

|}

+

This register triggers drawing vertex array elements.

+

=== GPUREG_VTX_FUNC ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)

+

|}

+

This register triggers clearing the post-vertex cache.

+

=== GPUREG_FIXEDATTRIB_INDEX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)

+

|}

+

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

+

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| colspan="2" | '''DATA0:'''

+

|-

+

| 0-7

+

| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)

+

|-

+

| 8-31

+

| float1.7.16, Vertex attribute element 4 (W)

+

|-

+

| colspan="2" | '''DATA1:'''

+

|-

+

| 0-15

+

| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)

+

|-

+

| 16-31

+

| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)

+

|-

+

| colspan="2" | '''DATA2:'''

+

|-

+

| 0-23

+

| float1.7.16, Vertex attribute element 1 (X)

+

|-

+

| 24-31

+

| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)

+

|}

+

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

+

=== GPUREG_CMDBUF_SIZE0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-20

+

| unsigned, Size of command buffer 0 >> 3

+

|}

+

This register sets the size of the first command buffer.

+

=== GPUREG_CMDBUF_SIZE1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-20

+

| unsigned, Size of command buffer 1 >> 3

+

|}

+

This register sets the size of the second command buffer.

+

=== GPUREG_CMDBUF_ADDR0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-28

+

| unsigned, Physical address of command buffer 0 >> 3

+

|}

+

This register sets the physical address of the first command buffer.

+

=== GPUREG_CMDBUF_ADDR1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-28

+

| unsigned, Physical address of command buffer 1 >> 3

+

|}

+

This register sets the physical address of the second command buffer.

+

=== GPUREG_CMDBUF_JUMP0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)

+

|}

+

This register triggers a jump to the first command buffer.

+

=== GPUREG_CMDBUF_JUMP1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)

+

|}

+

This register triggers a jump to the second command buffer.

+

=== GPUREG_VSH_NUM_ATTR ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Number of vertex shader input attributes - 1

+

|}

+

This register sets the number of vertex shader input attributes.

+

=== GPUREG_VSH_COM_MODE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)

+

|}

+

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

+

When disabled and the geometry unit is not in use, as configured by GPUREG_GEOSTAGE_CONFIG, uniforms, outmap mask, program code and swizzle data are propagated to the geometry shader unit.

+

=== GPUREG_START_DRAW_FUNC0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Mode (0 = drawing, 1 = configuration)

+

|-

+

| 1-7

+

| 0x0

+

|}

+

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

+

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Number of vertex shader output map registers - 1

+

|}

+

This register sets the number of vertex shader output map registers.

+

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Number of vertex shader output map registers - 1

+

|}

+

This register sets the number of vertex shader output map registers.

+

=== GPUREG_GSH_MISC0 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)

+

|}

+

This register configures miscellaneous geometry shader properties.

+

=== GPUREG_GEOSTAGE_CONFIG2 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)

+

|-

+

| 8

+

| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)

+

|}

+

This register configures the geometry stage of the GPU pipeline.

+

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

+

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

+

=== GPUREG_GSH_MISC1 ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-4

+

| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)

+

|}

+

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

+

=== GPUREG_PRIMITIVE_CONFIG ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Number of vertex shader output map registers - 1

+

|-

+

| 8-9

+

| unsigned, Primitive mode

+

|}

+

This register configures primitive drawing.

+

Primitive mode value:

+

{| class="wikitable" border="1"

+

! Value

+

! Description

+

|-

+

| 0

+

| Triangles

+

|-

+

| 1

+

| Triangle strip

+

|-

+

| 2

+

| Triangle fan

+

|-

+

| 3

+

| Geometry primitive

+

|}

+

=== GPUREG_RESTART_PRIMITIVE ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Trigger (0 = idle, 1 = reset primitive)

+

|-

+

| 1-31

+

| 0x0

+

|}

+

This register triggers resetting primitive drawing.

+

== Shader registers ==

+

=== GPUREG_''SH''_BOOLUNIFORM ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Boolean register b0 value (0 = false, 1 = true)

+

|-

+

| 1

+

| unsigned, Boolean register b1 value (0 = false, 1 = true)

+

|-

+

| 2

+

| unsigned, Boolean register b2 value (0 = false, 1 = true)

+

|-

+

| 3

+

| unsigned, Boolean register b3 value (0 = false, 1 = true)

+

|-

+

| 4

+

| unsigned, Boolean register b4 value (0 = false, 1 = true)

+

|-

+

| 5

+

| unsigned, Boolean register b5 value (0 = false, 1 = true)

+

|-

+

| 6

+

| unsigned, Boolean register b6 value (0 = false, 1 = true)

+

|-

+

| 7

+

| unsigned, Boolean register b7 value (0 = false, 1 = true)

+

|-

+

| 8

+

| unsigned, Boolean register b8 value (0 = false, 1 = true)

+

|-

+

| 9

+

| unsigned, Boolean register b9 value (0 = false, 1 = true)

+

|-

+

| 10

+

| unsigned, Boolean register b10 value (0 = false, 1 = true)

+

|-

+

| 11

+

| unsigned, Boolean register b11 value (0 = false, 1 = true)

+

|-

+

| 12

+

| unsigned, Boolean register b12 value (0 = false, 1 = true)

+

|-

+

| 13

+

| unsigned, Boolean register b13 value (0 = false, 1 = true)

+

|-

+

| 14

+

| unsigned, Boolean register b14 value (0 = false, 1 = true)

+

|-

+

| 15

+

| unsigned, Boolean register b15 value (0 = false, 1 = true)

+

|-

+

| 16-31

+

| 0x7FFF

+

|}

+

This register is used to set a shader unit's boolean registers.

+

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Integer register i''i'' X value

+

|-

+

| 8-15

+

| unsigned, Integer register i''i'' Y value

+

|-

+

| 16-23

+

| unsigned, Integer register i''i'' Z value

+

|-

+

| 24-31

+

| unsigned, Integer register i''i'' W value

+

|}

+

These registers are used to set a shader unit's integer registers.

+

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Input vertex attributes - 1

+

|-

+

| 8-15

+

| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)

+

|-

+

| 16-23

+

| 0x0

+

|-

+

| 24-31

+

| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)

+

|}

+

This register is used to configure a shader unit's input buffer.

+

=== GPUREG_''SH''_ENTRYPOINT ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-15

+

| unsigned, Code entry point offset, in 32-bit words

+

|-

+

| 16-31

+

| 0x7FFF

+

|}

+

This register sets a shader unit's code entry point.

+

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

+

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

+

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Vertex attribute 0 input register index

+

|-

+

| 4-7

+

| unsigned, Vertex attribute 1 input register index

+

|-

+

| 8-11

+

| unsigned, Vertex attribute 2 input register index

+

|-

+

| 12-15

+

| unsigned, Vertex attribute 3 input register index

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|-

+

| 16-19

+

| unsigned, Vertex attribute 4 input register index

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|-

+

| 20-23

+

| unsigned, Vertex attribute 5 input register index

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|-

+

| 24-27

+

| unsigned, Vertex attribute 6 input register index

+

|-

+

| 28-31

+

| unsigned, Vertex attribute 7 input register index

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|}

+

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

+

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

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{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-3

+

| unsigned, Vertex attribute 8 input register index

+

|-

+

| 4-7

+

| unsigned, Vertex attribute 9 input register index

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|-

+

| 8-11

+

| unsigned, Vertex attribute 10 input register index

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|-

+

| 12-15

+

| unsigned, Vertex attribute 11 input register index

+

|-

+

| 16-19

+

| unsigned, Vertex attribute 12 input register index

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|-

+

| 20-23

+

| unsigned, Vertex attribute 13 input register index

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|-

+

| 24-27

+

| unsigned, Vertex attribute 14 input register index

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|-

+

| 28-31

+

| unsigned, Vertex attribute 15 input register index

+

|}

+

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

+

=== GPUREG_''SH''_OUTMAP_MASK ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0

+

| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 1

+

| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 2

+

| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 3

+

| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 4

+

| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 5

+

| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 6

+

| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)

+

|-

+

| 7

+

| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 8

+

| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 9

+

| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 10

+

| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 11

+

| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 12

+

| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 13

+

| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 14

+

| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 15

+

| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)

+

|-

+

| 16-31

+

| 0x0

+

|}

+

This register toggles a shader unit's output registers.

+

=== GPUREG_''SH''_CODETRANSFER_END ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| unsigned, Signal transfer end (0 = idle, non-zero = signal)

+

|}

+

This register's value should be set to 1 in order to finalize the transfer of shader code.

+

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-7

+

| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)

+

|-

+

| 31

+

| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)

+

|}

+

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

+

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-31

+

| Floating-point register component data

+

|}

+

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

+

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:

+

** first word : ZZWWWWWW

+

** second word : YYYYZZZZ

+

** third word : XXXXXXYY

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* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

+

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

+

{| class="wikitable" border="1"

+

! Bits

+

! Description

+

|-

+

| 0-11

+

| unsigned, Target shader code offset

|}

−

This register ~~sets~~ the ~~target float vec4 vertex~~ shader ~~uniform ID and transfer mode for the~~ data ~~transfer system. As such it is typically used right before~~ [[#~~GPUREG_VSH_FLOATUNIFORM_DATA~~|~~GPUREG_VSH_FLOATUNIFORM_DATA~~]]~~, though writing to one register does not make writing to the other mandatory~~.

+

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

−

=== ~~GPUREG_VSH_FLOATUNIFORM_DATA~~ ===

+

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"

Line 5,264: Line 8,177:

|-

| 0-31

−

| ~~Float vec4 vertex shader uniform~~ data~~. (format depends on transfer mode, see below for details)~~

+

| unsigned, Shader instruction data

|}

−

This register is used to ~~set the value of float vec4 vertex~~ shader ~~uniform registers. The~~ data ~~format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]~~. This register ~~functions~~ as a FIFO queue : ~~after~~ each ~~time a uniform~~ register ~~is successfully set,~~ the ~~target uniform ID~~ value ~~is incremented, meaning that groups of uniforms with contiguous register IDs can be~~ set ~~with only one initial write to~~ [[#~~GPUREG_VSH_FLOATUNIFORM_CONFIG~~|~~GPUREG_VSH_FLOATUNIFORM_CONFIG~~]].

+

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

−

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in ~~the reverse order. Assuming~~ each ~~letter corresponds~~ to ~~4 bits, the format becomes :~~

−

** first word : ZZWWWWWW

−

** second word : YYYYZZZZ

−

** third word : XXXXXXYY

−

* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register~~'s 4 components, in the reverse order~~.

−

=== ~~GPUREG_VSH_CODETRANSFER_CONFIG~~ ===

+

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"

Line 5,282: Line 8,189:

|-

| 0-11

−

| ~~Target vertex shader code offset for data transfer.~~

+

| unsigned, Target shader operand descriptor offset

−

|}

−

~~This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.~~

−

~~NOTE : as we do not yet know what a shader program's maximum size is yet~~, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.

−

~~=== GPUREG_VSH_CODETRANSFER_DATA ===~~

−

~~{| class="wikitable" border="1"~~

−

~~! Bits~~

−

~~! Description~~

−

|-

−

~~| 0-31~~

−

~~| Vertex shader instruction data.~~

−

|}

−

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.

−

~~=== GPUREG_VSH_OPDESCS_CONFIG ===~~

−

~~{| class="wikitable" border="1"~~

−

~~! Bits~~

−

~~! Description~~

−

|-

−

~~| 0-6~~

−

| Target ~~vertex~~ shader operand descriptor offset ~~for data transfer.~~

|}

−

This register is used to set the offset at which upcoming ~~vertex~~ shader operand descriptor data transferred through [[#~~GPUREG_VSH_OPDESCS_DATA~~|~~GPUREG_VSH_OPDESCS_DATA~~]] should be written.

+

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

−

=== ~~GPUREG_VSH_OPDESCS_DATA~~ ===

+

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"

Line 5,320: Line 8,201:

|-

| 0-31

−

| ~~Vertex shader~~ operand descriptor data.

+

| unsigned, Shader operand descriptor data

|}

−

This register is used to transfer ~~vertex~~ shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU ~~vertex~~ shader operand descriptor memory bank at the offset initially set by [[#~~GPUREG_VSH_OPDESCS_CONFIG~~|~~GPUREG_VSH_OPDESCS_CONFIG~~]]. The offset in question is incremented after each write to this register.

+

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

−

~~[[Category:GPU]]~~

Emufan4568

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Changes

GPU/Internal Registers (edit)

Revision as of 18:36, 24 January 2024