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GPU/Internal Registers (edit)

Revision as of 18:36, 24 January 2024

991 bytes added ,  24 January
Update GPUREG_VSH_COM_MODE from hardware findings
Line 26: Line 26:  
| Parameter mask
 
| Parameter mask
 
|-
 
|-
−
| 20-30
+
| 20-27
 
| Number of extra parameters (may be zero)
 
| Number of extra parameters (may be zero)
 +
|-
 +
| 28-30
 +
| Unused
 
|-
 
|-
 
| 31
 
| 31
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=== Aliases ===
 
=== Aliases ===
   −
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]
+
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]
    
=== Data Types ===
 
=== Data Types ===
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|-
 
|-
 
| 0233
 
| 0233
−
| [[#GPUREG_FIXEDATTRIB_DATA0|GPUREG_FIXEDATTRIB_DATA0]]
+
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
 
|?
 
|?
 
|PICA_REG_VS_FIXED_ATTR_DATA0
 
|PICA_REG_VS_FIXED_ATTR_DATA0
 
|-
 
|-
 
| 0234
 
| 0234
−
| [[#GPUREG_FIXEDATTRIB_DATA1|GPUREG_FIXEDATTRIB_DATA1]]
+
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
 
|?
 
|?
 
|PICA_REG_VS_FIXED_ATTR_DATA1
 
|PICA_REG_VS_FIXED_ATTR_DATA1
 
|-
 
|-
 
| 0235
 
| 0235
−
| [[#GPUREG_FIXEDATTRIB_DATA2|GPUREG_FIXEDATTRIB_DATA2]]
+
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
 
|?
 
|?
 
|PICA_REG_VS_FIXED_ATTR_DATA2
 
|PICA_REG_VS_FIXED_ATTR_DATA2
Line 4,158: Line 4,161:     
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
 
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
 +
 +
Semantics that have not been mapped to a component of an output register have a value of 1
    
Semantic values:
 
Semantic values:
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|-
 
|-
 
| 0-9
 
| 0-9
−
| unsigned, X
+
| signed, X
 
|-
 
|-
 
| 16-25
 
| 16-25
−
| unsigned, Y
+
| signed, Y
 
|}
 
|}
   Line 4,563: Line 4,568:  
|-
 
|-
 
| 4-5
 
| 4-5
−
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
+
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
 
|-
 
|-
 
| 8-10
 
| 8-10
Line 4,717: Line 4,722:  
|-
 
|-
 
| 0
 
| 0
−
| unsigned, Perspective (0 = not perspective, 1 = perspective)
+
| unsigned, Perspective (0 = perspective, 1 = not perspective)
 
|-
 
|-
 
| 1-23
 
| 1-23
Line 4,896: Line 4,901:  
|-
 
|-
 
| 1
 
| 1
−
| U2
+
| U²
 
|-
 
|-
 
| 2
 
| 2
Line 4,902: Line 4,907:  
|-
 
|-
 
| 3
 
| 3
−
| V2
+
| V²
 
|-
 
|-
 
| 4
 
| 4
−
| U + V
+
| (U + V) / 2
 
|-
 
|-
 
| 5
 
| 5
−
| U2 + V2
+
| (U² + V²) / 2
 
|-
 
|-
 
| 6
 
| 6
−
| sqrt(U2*U2 + V2*V2)
+
| sqrt(U² + V²)
 
|-
 
|-
 
| 7
 
| 7
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| unsigned, Minification filter
 
| unsigned, Minification filter
 
|-
 
|-
−
| 3-10
+
| 3-6
−
| 0x60
+
| Min LOD (usually 0)
 +
|-
 +
| 7-10
 +
| Max LOD (usually 6)
 
|-
 
|-
 
| 11-18
 
| 11-18
Line 5,037: Line 5,045:  
|-
 
|-
 
| 0-7
 
| 0-7
−
| unsigned, Texture offset
+
| unsigned, Texture offset (Mipmap level 0 / base level)
 +
|-
 +
| 8-15
 +
| unsigned, mipmap level 1 offset (usually 0x80)
 
|-
 
|-
−
| 8-31
+
| 16-23
−
| 0xE0C080
+
| unsigned, mipmap level 2 offset (usually 0xC0)
 +
|-
 +
| 24-31
 +
| unsigned, mipmap level 3 offset (usually 0xE0)
 
|}
 
|}
   −
This register is used to set the procedural texture unit's offset.
+
This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .
    
=== GPUREG_PROCTEX_LUT ===
 
=== GPUREG_PROCTEX_LUT ===
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|-
 
|-
 
| 12-23
 
| 12-23
−
| fixed1.0.11, Difference from next element
+
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
 
|}
 
|}
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|-
 
|-
 
| 12-23
 
| 12-23
−
| fixed1.0.11, Difference from next element
+
| fixed0.0.12 with two's complement, Difference from next element
 
|}
 
|}
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|-
 
|-
 
| 12-23
 
| 12-23
−
| fixed1.0.11, Difference from next element
+
| fixed0.0.12 with two's complement, Difference from next element
 
|}
 
|}
   Line 5,164: Line 5,178:  
|-
 
|-
 
| 0-7
 
| 0-7
−
| fixed1.0.7, Red difference between current and next color table elements
+
| signed, Half of red difference between current and next color table elements
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| fixed1.0.7, Green difference between current and next color table elements
+
| signed, Half of green difference between current and next color table elements
 
|-
 
|-
 
| 16-23
 
| 16-23
−
| fixed1.0.7, Blue difference between current and next color table elements
+
| signed, Half of blue difference between current and next color table elements
 
|-
 
|-
 
| 24-31
 
| 24-31
−
| fixed1.0.7, Alpha difference between current and next color table elements
+
| signed, Half of alpha difference between current and next color table elements
 
|}
 
|}
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| Previous
 
| Previous
 
|}
 
|}
 +
 +
Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.
    
=== GPUREG_TEXENV''i''_OPERAND ===
 
=== GPUREG_TEXENV''i''_OPERAND ===
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This register is used to configure the blending function.
 
This register is used to configure the blending function.
   −
Equation values:
+
'''Equation values:'''
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 5,725: Line 5,741:  
|}
 
|}
   −
Function values:
+
Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)
 +
 
 +
'''Function values:'''
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 6,047: Line 6,065:     
This register is used to depth testing and framebuffer write masking.
 
This register is used to depth testing and framebuffer write masking.
 +
 +
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.
    
Depth function values:
 
Depth function values:
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| 0-7
 
| 0-7
 
| unsigned, View shading effect in line-of-sight direction
 
| unsigned, View shading effect in line-of-sight direction
 +
|-
 +
| 8
 +
| Gas color LUT input
 
|}
 
|}
   −
This register configures gas light shading in the line-of-sight direction.
+
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.
 +
 
 +
Color LUT input values:
 +
 
 +
{| class="wikitable" border="1"
 +
! Value
 +
! Description
 +
|-
 +
| 0
 +
| Gas density
 +
|-
 +
| 1
 +
| Light factor
 +
|}
    
=== GPUREG_GAS_LUT_INDEX ===
 
=== GPUREG_GAS_LUT_INDEX ===
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| 0-23
 
| 0-23
 
| fixed0.16.8, Depth direction attenuation proportion
 
| fixed0.16.8, Depth direction attenuation proportion
 +
|-
 +
| 24-25
 +
| unsigned, Depth function
 
|}
 
|}
   −
This register is used to configure the gas depth direction attenuation proportion.
+
This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.
 +
 
 +
Gas depth function values:
 +
 
 +
{| class="wikitable" border="1"
 +
! Value
 +
! Description
 +
|-
 +
| 0
 +
| Never
 +
|-
 +
| 1
 +
| Always
 +
|-
 +
| 2
 +
| Greater than/Greater than or equal
 +
|-
 +
| 3
 +
| Less than/Less than or equal/Equal/Not equal
 +
|}
    
=== GPUREG_FRAGOP_SHADOW ===
 
=== GPUREG_FRAGOP_SHADOW ===
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| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
 
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
 
|-
 
|-
−
| 20-22
+
| 20
−
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
+
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
 
|-
 
|-
 
| 21
 
| 21
−
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
+
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
 
|-
 
|-
 
| 22
 
| 22
−
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
+
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
 
|-
 
|-
 
| 24
 
| 24
Line 7,545: Line 7,603:  
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.
 
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.
   −
=== GPUREG_FIXEDATTRIB_DATA0 ===
+
=== GPUREG_FIXEDATTRIB_DATA''i'' ===
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 7,551: Line 7,609:  
! Description
 
! Description
 
|-
 
|-
−
| 0-23
+
| colspan="2" | '''DATA0:'''
−
| float1.7.16, Vertex attribute element 1
+
|-
 +
| 0-7
 +
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
 +
|-
 +
| 8-31
 +
| float1.7.16, Vertex attribute element 4 (W)
 +
|-
 +
| colspan="2" | '''DATA1:'''
 
|-
 
|-
−
| 24-31
+
| 0-15
−
| float1.7.16, Vertex attribute element 2 (lower 8 bits)
+
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
−
|}
  −
 
  −
Accepts the first part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
  −
 
  −
=== GPUREG_FIXEDATTRIB_DATA1 ===
  −
 
  −
{| class="wikitable" border="1"
  −
! Bits
  −
! Description
   
|-
 
|-
−
| 0-23
+
| 16-31
−
| float1.7.16, Vertex attribute element 2 (upper 16 bits)
+
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
 
|-
 
|-
−
| 24-31
+
| colspan="2" | '''DATA2:'''
−
| float1.7.16, Vertex attribute element 3 (lower 16 bits)
  −
|}
  −
 
  −
Accepts the second part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
  −
 
  −
=== GPUREG_FIXEDATTRIB_DATA2 ===
  −
 
  −
{| class="wikitable" border="1"
  −
! Bits
  −
! Description
   
|-
 
|-
 
| 0-23
 
| 0-23
−
| float1.7.16, Vertex attribute element 3 (upper 8 bits)
+
| float1.7.16, Vertex attribute element 1 (X)
 
|-
 
|-
 
| 24-31
 
| 24-31
−
| float1.7.16, Vertex attribute element 4
+
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
 
|}
 
|}
   −
Accepts the third part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
+
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
    
=== GPUREG_CMDBUF_SIZE0 ===
 
=== GPUREG_CMDBUF_SIZE0 ===
Line 7,685: Line 7,731:     
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.
 
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.
 +
When disabled and the geometry unit is not in use, as configured by GPUREG_GEOSTAGE_CONFIG, uniforms, outmap mask, program code and swizzle data are propagated to the geometry shader unit.
    
=== GPUREG_START_DRAW_FUNC0 ===
 
=== GPUREG_START_DRAW_FUNC0 ===
Emufan4568
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