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=== Vertex attribute alignment ===
=== Vertex attribute alignment ===
Vertex components which are defined through [[GPU/Internal_Registers#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFERi_CONFIG1]] will be aligned.
Vertex components which are defined through [[GPU/Internal_Registers#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFERi_CONFIG1]] will be accessed aligned by the GPU.
* Vertex attributes will be aligned to their component element size.
* Vertex attributes will be aligned to their component element size.
* Padding attributes (Component type > 11) will always aligned to 4 byte offets into the buffer.
* Padding attributes (Component type > 11) will always aligned to 4 byte offets into the buffer.
* The stride which is passed to the GPU should be passed unaligned.
=== Vertex stride in GPUREG_ATTRIBBUFFERi_CONFIG2 ===
=== Vertex stride in GPUREG_ATTRIBBUFFERi_CONFIG2 ===
=== Output mapping in GPUREG_SH_OUTMAP_MASK ===
=== Output mapping in GPUREG_SH_OUTMAP_MASK ===
The output masking in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] influences how the registers starting at [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] will map to outputs in the shader.
The output masking in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] influences how the registers starting at [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] map to outputs in the shader.
If an output is disabled in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] it means that no slot in the [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] registers is consumed.
If an output is disabled in [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_MASK|GPUREG_SH_OUTMAP_MASK]] it means that no slot in the [[GPU/Internal_Registers#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_Oi]] registers is consumed.
== Shaders ==
== Shaders ==
=== Write output components exactly once ===
=== Configued Output components must be written exactly once ===
Each configured output component has to be written exactly once or the PICA freezes.
Each configured output component has to be written exactly once or the PICA freezes.