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GPU/Shader Instruction Set (edit)

Revision as of 15:45, 24 January 2015

34 bytes added ,  15:45, 24 January 2015
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Line 392: Line 392:  
|  1u
 
|  1u
 
|  MOVA
 
|  MOVA
−
|  Address Register Load; sets (a0.x, a0.y, _, _) to SRC1 (cast to integer).
+
|  Address Register Load; sets (a0.x, a0.y, _, _) to SRC1 (cast to integer by truncating the fractional part).
 
|-
 
|-
 
|  0x13
 
|  0x13
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