Changes

Jump to navigation Jump to search
272 bytes added ,  05:12, 11 December 2015
m
Line 127: Line 127:  
|-
 
|-
 
| 7
 
| 7
| Flag: when source buffer is not located in VRAM and this flag is non-zero, svcFlushProcessDataCache is used with the source buffer.
+
| Flush source (0 = don't flush, 1 = flush)
 
|}
 
|}
   −
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM.
+
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer.
    
== Trigger Command List Processing ==
 
== Trigger Command List Processing ==
Line 148: Line 148:  
|-
 
|-
 
| 3
 
| 3
| Flag, bit0 is written to GSP module state
+
| Update gas additive blend results (0 = don't update, 1 = update)
 
|-
 
|-
 
| 6-4
 
| 6-4
Line 154: Line 154:  
|-
 
|-
 
| 7
 
| 7
| When non-zero, call svcFlushProcessDataCache() with the specified buffer
+
| Flush buffer (0 = don't flush, 1 = flush)
 
|}
 
|}
   −
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU_Commands|GPU commands]].
+
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.
    
== Trigger Memory Fill ==
 
== Trigger Memory Fill ==
Line 187: Line 187:  
|-
 
|-
 
| 7
 
| 7
| The low u16 is control0, while the high u16 is control1
+
| Control0 <nowiki>|</nowiki> (Control1 << 16)
 
|}
 
|}
   −
This commands converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
+
This command converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
 
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
 
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
   −
The values of control0 and control1 give information about the type of memory fill and if it has to be triggered. By default the fill pattern is set to 16bits.
+
The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters.
 
  −
{| class="wikitable" border="1"
  −
|-
  −
!  Bit
  −
!  Description
  −
|-
  −
| 0
  −
| trigger
  −
|-
  −
| 8
  −
| Fill pattern of 24bits
  −
|-
  −
| 9
  −
| Fill pattern of 32bits
  −
|}
      
== Trigger Display Transfer ==
 
== Trigger Display Transfer ==
Line 256: Line 241:  
|-
 
|-
 
| 1
 
| 1
| Input buffer address
+
| Input buffer address.
 
|-
 
|-
 
| 2
 
| 2
| Output buffer address
+
| Output buffer address.
 
|-
 
|-
 
| 3
 
| 3
| Size
+
| Total bytes to copy, not including gaps.
 
|-
 
|-
 
| 4
 
| 4
| Input [[GPU|dimensions]]?
+
| Bits 0-15: Size of input line, in bytes. Bits 16-31: Gap between input lines, in bytes.
 
|-
 
|-
 
| 5
 
| 5
| Output dimensions?
+
| Same as 4, but for the output.
 
|-
 
|-
 
| 6
 
| 6
| Flags, normally this is 0x8, with bit2 optionally set when either of the dimensions fields are set.
+
| Flags, corresponding to the [[GPU/External_Registers#Transfer_Engine|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is always set, bit 2 is set if any output dimension is smaller than the input, and other bits are always 0.
 
|-
 
|-
 
| 7
 
| 7
Line 277: Line 262:  
|}
 
|}
   −
This command is similar to cmd3. It also writes to the [[GPU]] registers at 0x1EF00C00. It's unknown where the difference is.
+
This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.
   −
== Prepare Command List Processing ==
+
== Flush Cache Regions ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
1,434

edits

Navigation menu