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Line 127: |
| |- | | |- |
| | 7 | | | 7 |
− | | Flag: when source buffer is not located in VRAM and this flag is non-zero, svcFlushProcessDataCache is used with the source buffer. | + | | Flush source (0 = don't flush, 1 = flush) |
| |} | | |} |
| | | |
− | This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. | + | This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer. |
| | | |
| == Trigger Command List Processing == | | == Trigger Command List Processing == |
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| |- | | |- |
| | 3 | | | 3 |
− | | Flag, bit0 is written to GSP module state | + | | Update gas additive blend results (0 = don't update, 1 = update) |
| |- | | |- |
| | 6-4 | | | 6-4 |
Line 154: |
Line 154: |
| |- | | |- |
| | 7 | | | 7 |
− | | When non-zero, call svcFlushProcessDataCache() with the specified buffer | + | | Flush buffer (0 = don't flush, 1 = flush) |
| |} | | |} |
| | | |
− | This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. | + | This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer. |
| | | |
| == Trigger Memory Fill == | | == Trigger Memory Fill == |
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| |- | | |- |
| | 7 | | | 7 |
− | | The low u16 is control0, while the high u16 is control1 (?) | + | | Control0 <nowiki>|</nowiki> (Control1 << 16) |
| |} | | |} |
| | | |
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| The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped. | | The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped. |
| | | |
− | The values of control0 and control1 give information about the type of memory fill. See [[GPU Registers#Memory Fill|here]] for more information about memory fill parameters. | + | The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters. |
| | | |
| == Trigger Display Transfer == | | == Trigger Display Transfer == |