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GSP Shared Memory (edit)

Revision as of 22:59, 15 October 2023

669 bytes added ,  22:59, 15 October 2023
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This page describes the structure of the GSP [[GSPGPU:RegisterInterruptRelayQueue|shared]] memory. GX commands and framebuffer info is stored here, and other unknown data.
+
This page describes the structure of the GSP [[GSPGPU:RegisterInterruptRelayQueue|shared]] memory. Interrupt, framebuffer, and GX command data is stored here.
    +
=Interrupt Queue=
   −
=Interrupt info=
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The Interrupt queue is located at sharedMemBase + (clientID * 0x40).
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The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.
  −
 
  −
It is a list of interrupts (id's 0-6 exist).
      
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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|-
 
|-
 
| 0x0
 
| 0x0
−
| Index of the last processed data (field size is 0x33) (must be updated manually)
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| Offset from the count where to save incoming interrupts
 
|-
 
|-
 
| 0x1
 
| 0x1
−
| To be processed datafields, (max 0x20 for PDC interrupts else the missed PDC filds are used,max 0x34 for all other if more interrupts happen and the Errorflag is 0 the Errorflag is set to 1)
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| Count (max 0x20 for PDC, 0x34 for others)
 
|-
 
|-
 
| 0x2
 
| 0x2
−
| Errorflag (if the first bit of Errorflag is set future PDC interrupts are ignored)
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| Missed other interrupts (set to 1 when 0 and count >= 0x34)
 
|-
 
|-
 
| 0x3
 
| 0x3
−
| not used
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| Flags (bit0 = skip PDC)
 
|-
 
|-
 
| 0x4-0x7
 
| 0x4-0x7
−
| missed PDC0
+
| Missed PDC0 (incremented when flags.bit0 is clear and count >= 0x20)
 
|-
 
|-
 
| 0x8-0xB
 
| 0x8-0xB
−
| missed PDC1
+
| Missed PDC1 (same as above)
 
|-
 
|-
 
| 0xC-0x3F
 
| 0xC-0x3F
−
| u8 Interrupttypefield (0=PSC0, 1=PSC1, 2=PDC0/VBlank1(send to all threads), 3=PDC1/VBlank2 (send to all threads), 4=PPF, 5=P3D, 6=DMA)
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| Interrupt list (u8) (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop, 3=PDC1/VBlankBottom, 4=PPF, 5=P3D, 6=DMA)
 
|}
 
|}
   −
=Framebuffer info=
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GSP fills the interrupt list, then triggers the event set with [[GSPGPU:RegisterInterruptRelayQueue|RegisterInterruptRelayQueue]] for the specified process(es).
−
The framebuffer info structure for the main LCD is located at sharedmemvadr + 0x200 + threadindex*0x80. The framebuffer info structure for the sub LCD is located at sharedmemvadr + 0x240 + threadindex*0x80.
+
 
 +
PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.
 +
 
 +
= Framebuffer Info =
 +
 
 +
The framebuffer info structure for the top LCD is located at sharedMemBase + 0x200 + (clientID * 0x80).
 +
 
 +
The framebuffer info structure for the bottom LCD is located at sharedMemBase + 0x240 + (clientID * 0x80).
 +
 
 +
== Framebuffer Info Header ==
   −
==Framebuffer info header==
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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|-
 
|-
 
| 1
 
| 1
−
| Flag
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| Flags (bit0 = client has set new data)
 
|-
 
|-
 
| 3-2
 
| 3-2
 
| Padding
 
| Padding
 +
|}
 +
 +
== Framebuffer Info Structure ==
 +
 +
{| class="wikitable" border="1"
 +
|-
 +
!  Index Word
 +
!  Description
 +
|-
 +
| 0
 +
| Active framebuffer (0 = first, 1 = second)
 +
|-
 +
| 1
 +
| Left framebuffer VA
 +
|-
 +
| 2
 +
| Right framebuffer VA (top screen only)
 +
|-
 +
| 3
 +
| [[GPU/External_Registers#LCD_Source_Framebuffer_Setup|Stride]] (offset 0x90)
 +
|-
 +
| 4
 +
| [[GPU/External_Registers#Framebuffer_format|Format]]
 +
|-
 +
| 5
 +
| [[GPU/External_Registers#LCD_Source_Framebuffer_Setup|Status]] (offset 0x78)
 +
|-
 +
| 6
 +
| ? ("Attribute")
 
|}
 
|}
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The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.
 
The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.
   −
=3D Slider and 3D [[GSPGPU:SetLedForceOff|LED]]=
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= 3D Slider and 3D [[GSPGPU:SetLedForceOff|LED]] =
 +
 
 
See [[Configuration Memory]].
 
See [[Configuration Memory]].
   −
=Command Buffer Header=
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= Command Queue =
   −
The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.
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The command queue is located at sharedMemBase + 0x800 + (clientID * 0x200). It consists of an header followed by at most 15 command entries. Each command entry is of size 0x20 and has an header followed by command specific parameters.
 +
 
 +
After adding a command, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing when the total commands field is value 1.
 +
 
 +
== Command Queue Header ==
    
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0
−
| Current command index. This index is updated by GSP module after loading the command data, right before the command is processed. When this index is updated by GSP module, the total commands field is decreased by one as well.
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| Index of the command to process, this is incremented by GSP before handling the command
 
|-
 
|-
−
| 1
+
| 1
−
| Total commands to process, must not be value 0 when GSP module handles commands. This must be <=15 when writing a command to shared memory. This is incremented by the application when writing a command to shared memory, after increasing this value [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] is only used if this field is value 1.
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| Total commands to process, this is incremented by the application when adding the command to the queue, and decremented by GSP before handling the command
 
|-
 
|-
−
| 2
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| 2
−
| Must not be value 1. When the error-code u32 is set, this u8 is set to value 0x80.
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| Flags (bit0 = completed?, bit7 = fatal error)
 
|-
 
|-
−
| 3
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| 3
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| Bit0 must not be set
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| ? (bit0 = set flags.bit0)
 
|-
 
|-
 
| 4
 
| 4
−
| u32 Error code for the last GX command which failed
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| Result code for the last GX command which failed
 
|}
 
|}
   −
=Command Header=
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== Command Header ==
 +
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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!  Description
 
!  Description
 
|-
 
|-
−
| 0
+
| 0
−
| Command ID
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| Command ID
 
|-
 
|-
−
| 2-1
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| 1
−
| ?
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| ?
 
|-
 
|-
−
| 3
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| 2
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| When non-zero GSP module may check flags for the specified cmdID, command handling is aborted when the flags are set. The corresponding flag for each CmdID is set once the command is handled by GSP module, this flag is likely cleared once the GPU finishes processing the command.
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| ? (bit0 = set queue.flags.bit0 after processing)
 +
|-
 +
| 3
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| When set, the command fails if GSP is busy handling any other command; otherwise, it only fails if GSP is busy handling a command of the same kind
 
|}
 
|}
   −
The command is located at cmdbuf + 0x20 + cmdindex*0x20, the size of each command is 0x20-bytes. The command parameters are located at command+4. Addresses specified in parameters are application vaddrs, these are usually located in either the process GSP [[Memory_layout|heap]] or VRAM. For applications these addresses are normally located in the GSP heap, while for other processes these addresses are located in VRAM. Addresses/sizes specified in parameters except for cmd0 and cmd5 must be 8-byte [[GPU|aligned]].
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== Commands ==
 +
 
 +
Addresses specified in parameters are virtual addresses. For applications these are normally located in GSP memory, while for other processes they are located in VRAM.
 +
 
 +
Address and size parameters except for command 0 and command 5 must be 8-byte aligned.
   −
=Commands=
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=== Trigger DMA Request ===
   −
==GX RequestDma==
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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|-
 
|-
 
| 7
 
| 7
−
| Flag: when source buffer is not located in VRAM and this flag is non-zero, svcFlushProcessDataCache is used with the source buffer.
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| Flush source (0 = don't flush, 1 = flush)
 
|}
 
|}
   −
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM.
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This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer.
 +
 
 +
=== Trigger Command List Processing ===
   −
==GX SetCommandList Last==
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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|-
 
|-
 
| 3
 
| 3
−
| Flag, bit0 is written to GSP module state
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| Update gas additive blend results (0 = don't update, 1 = update)
 
|-
 
|-
 
| 6-4
 
| 6-4
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|-
 
|-
 
| 7
 
| 7
−
| When non-zero, call svcFlushProcessDataCache() with the specified buffer
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| Flush buffer (0 = don't flush, 1 = flush)
 
|}
 
|}
   −
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU_Commands|GPU commands]].
+
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.
 +
 
 +
=== Trigger Memory Fill ===
   −
==GX SetMemoryFill==
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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|-
 
|-
 
| 1
 
| 1
−
| Buf0 start address
+
| Buf0 start address (0 = don't fill anything)
 
|-
 
|-
 
| 2
 
| 2
Line 178: Line 227:  
|-
 
|-
 
| 4
 
| 4
−
| Buf1 start address
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| Buf1 start address (0 = don't fill anything)
 
|-
 
|-
 
| 5
 
| 5
Line 187: Line 236:  
|-
 
|-
 
| 7
 
| 7
−
| The low u16 is width0, while the high u16 is width1 (?)
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| Control0 <nowiki>|</nowiki> (Control1 << 16)
 
|}
 
|}
   −
This commands converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
+
This command converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
 
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
 
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
   −
==GX SetDisplayTransfer==
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The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters.
 +
 
 +
=== Trigger Display Transfer ===
 +
 
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers.
 
The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers.
   −
Flags:
+
Display transfers are performed asynchronously, so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data.
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* bit12-14 seem to be the output color format. Unknown if there are also bits for the input color format or if it's always RGBA8888.
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* when bit3 is set, no tiled->linear conversion is done, instead the buffer is copied linearly.
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Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly.
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* when bit1 is set, the buffer is converted from linear to tiled. This can be used to upload textures stored linearly. (bit3 has priority over bit1)
+
 
−
* when bit0 is set, the buffer is mirrored vertically during the copy.
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=== Trigger Texture Copy ===
   −
==GX SetTextureCopy==
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
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|-
 
|-
 
| 1
 
| 1
−
| Input buffer address
+
| Input buffer address.
 
|-
 
|-
 
| 2
 
| 2
−
| Output buffer address
+
| Output buffer address.
 
|-
 
|-
 
| 3
 
| 3
−
| Size
+
| Total bytes to copy, not including gaps.
 
|-
 
|-
 
| 4
 
| 4
−
| Input [[GPU|dimensions]]?
+
| Bits 0-15: Size of input line, in bytes. Bits 16-31: Gap between input lines, in bytes.
 
|-
 
|-
 
| 5
 
| 5
−
| Output dimensions?
+
| Same as 4, but for the output.
 
|-
 
|-
 
| 6
 
| 6
−
| Flags, normally this is 0x8, with bit2 optionally set when either of the dimensions fields are set.
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| Flags, corresponding to the [[GPU/External_Registers#Transfer_Engine|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is always set, bit 2 is set if any output dimension is smaller than the input, and other bits are always 0.
 
|-
 
|-
 
| 7
 
| 7
Line 262: Line 313:  
|}
 
|}
   −
This command is similar to cmd3, this command also writes to the [[GPU]] registers at 0x1EF00C00.
+
This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.
 +
 
 +
=== Flush Cache Regions ===
   −
==GX SetCommandList First ==
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
|-
 
|-
Kynex7510
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