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Line 5: − + − On New3DS models, there is instead 4x MPCore, 4x VFPv2, and 268-804MHz CPU.+ + − + + + + + + + − |- − | VRAM || 6 MB within SoC. − The above clock-rates were calculated by calling svcGetSystemTick in sets of 5(call it, execute svcSleepThread for 1s, then call it again), then the average of those were calculated. The clock-rate listed above applies for *all* 4 New3DS MPCores. − + + + + + Line 33:
Line 40: − + − Toshiba THGBMBG4P1KBAIT 2GB (MLC) − − Toshiba THGBMBG4P1KBAIT (MLC) − + + + + + + Line 51:
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→Specifications
This page lists and describes the hardware found inside the Nintendo 3DS. Many of these parts are custom made and are expanded upon here or in other pages.
This page lists and describes the hardware found inside the Nintendo 3DS. Many of these parts are custom made and are expanded upon here or in other pages.
== Common hardware ==
== Common hardware ==
! Type !! Description
! Type !! Description
|-
|-
| ARM11 Processor Core || [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/index.html ARM11 2x MPCore & 2x VFPv2 Co-Processor] 268MHz(~268123480 Hz).
| ARM11 Processor Core || Old3DS: [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/index.html ARM11 2x MPCore & 2x VFPv2 Co-Processor] 268MHz (268,111,856.0 ± 2<sup>-32</sup> Hz, i.e. exactly twice the clock rate of the ARM9).
New3DS: 4x MPCore, 4x VFPv2, able to run up to 804MHz (see below). It also has an optional 2MB L2 cache.
|-
|-
| ARM9 Processor Core || [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0201d/index.html ARM946] 134MHz(~134058675 Hz),
| ARM9 Processor Core || [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0201d/index.html ARM946] 134MHz (134,055,927.9 ± 2<sup>-32</sup> Hz),
|-
|-
| GPU || [http://en.wikipedia.org/wiki/PICA200 DMP PICA] 268MHz,
| GPU || [http://en.wikipedia.org/wiki/PICA200 DMP PICA] 268MHz,
|-
| VRAM || 6 MB within SoC.
|-
| Top screen || 800x240, with only 400 usable pixels per eye per line.
|-
| Bottom screen || 320x240, with resistive touch overlay.
|-
|-
| DSP || [https://twitter.com/CEVADSP/status/177172880918986752 CEVA TeakLite]. 134Mhz. 24ch 32728Hz sampling rates.
| DSP || [https://twitter.com/CEVADSP/status/177172880918986752 CEVA TeakLite]. 134Mhz. 24ch 32728Hz sampling rates.
|}
|}
New3DS exclusives are able to clock the CPU at 804MHz, but this appears to be limited to the currently running application/app cores. (timed by running svcGetSystemTick on either side of a long idle loop to stay in the current process context. svcSleepThread + svcGetSystemTick implies a tick counter running at 268mhz in this mode.)
New3DS exclusives are able to clock the CPU at 804MHz, but this appears to be limited to the currently running application/app cores. Timed by running svcGetSystemTick on either side of a long idle loop to stay in the current process context. svcGetSystemTick uses a tick counter running at 268MHz in this mode.
On New3DS: when Home Menu is active, the system runs at 804MHz. For everything else, it's 268MHz, except when the app(let) has the required flag set. See [[NCCH/Extended_Header|here]] and [[PDN_Registers|here]] for details, regarding clock-rate and cache.
For New3DS-only there are multiple clock-rate multiplier values available in [[PDN_Registers|hardware]], but since the relevant code is only implemented in the New3DS ARM11-kernel, the only non-normal clock-rate available with official kernel code is 3x.
== Specifications ==
== Specifications ==
| FCRAM || [http://www.fujitsu.com/downloads/MICRO/fma/pdf/MB81EDS516545_e511463.pdf 2x64MB Fujitsu MB82M8080-07L] || Fujitsu MB82DBS16641 || Fujitsu MB82DBS1664 || ?? || Fujitsu MB82MK9A9A
| FCRAM || [http://www.fujitsu.com/downloads/MICRO/fma/pdf/MB81EDS516545_e511463.pdf 2x64MB Fujitsu MB82M8080-07L] || Fujitsu MB82DBS16641 || Fujitsu MB82DBS1664 || ?? || Fujitsu MB82MK9A9A
|-
|-
| Storage || Toshiba THGBM2G3P1FBAI8 1GB || ?? || Toshiba THGBM4G3P1H8BAIR 1GB || Samsung KLM4G1YEQC 4GB (in 1.3GiB SLC mode)
| Top Screen || 3.53 in, 3D || 4.88 in, 3D || 3.53 in(?) cropped from a single panel || 3.88 in, 3D || 4.88 in, 3D
|| Samsung KLM4G1YEMD-B031 4GB (in 1.3GiB SLC mode)
|-
|-
| Audio Codec || TI PAIC3010B 0AA37DW || ?? || ?? || TI AIC3010B 39C4ETW || TI AIC3010D 48C01JW
| Bottom Screen || 3.00 in || 4.18 in || 3.00 in(?) cropped from a single panel || 3.33 in || 4.18 in
|-
| Storage ||colspan="3"| Toshiba THGBM2G3P1FBAI8 1GB ||colspan="2"| Samsung KLM4G1YEQC 4GB (in 1.3GiB SLC mode)
Toshiba THGBMBG4P1KBAIT 2GB (MLC, approx. 1.8GiB usable)
|-
| Speaker, Microphone, Circlepad, Touch controller || TI PAIC3010B 0AA37DW || ?? || ?? || TI AIC3010B 39C4ETW || TI AIC3010D 48C01JW
|-
|-
| Gyroscope || [http://dl-web.dropbox.com/u/20520664/references/PS-ITG-3200-00-01.4.pdf Invensense ITG-3270 MEMS Gyroscope] || ?? || ?? || ?? || ??
| Gyroscope || [http://dl-web.dropbox.com/u/20520664/references/PS-ITG-3200-00-01.4.pdf Invensense ITG-3270 MEMS Gyroscope] || ?? || ?? || ?? || ??
|-
|-
| PMIC? || TI 93045A4 OAAH86W || ?? || ?? || TI 93045A4 38A6TYW G2 || TI 93045A4 49AF3NW G2
| PMIC? || TI 93045A4 OAAH86W || ?? || ?? || TI 93045A4 38A6TYW G2 || TI 93045A4 49AF3NW G2
|-
| Wifi SPI Flash
| Raw ID data: 20 58 || ?? || ?? || Raw ID data: 62 62 || ??
|}
|}
* [12] This IC is somewhat similar to [http://www.alldatasheet.net/datasheet-pdf/pdf/347838/NXP/SC16IS750IBS.html this].
* [12] This IC is somewhat similar to [http://www.alldatasheet.net/datasheet-pdf/pdf/347838/NXP/SC16IS750IBS.html this].
* The Raw ID data for Wifi SPI Flash is from command 0x9F, RDID.
== FCRAM ==
== FCRAM ==
This is the interface for the 'NEW' WiFi module (based on Atheros AR6002) first included in DSi.
This is the interface for the 'NEW' WiFi module (based on Atheros AR6002) first included in DSi.
The proprietary and by now ancient DS-mode WiFi is colored yellow, pins are unknown.
The proprietary DS-mode WiFi is colored yellow, pins are unknown.
I²C eeprom is colored blue:
* SCL
* SCL
* SDA
* SDA
* NC
* NC
=== Auxiliary Microntroller ===
=== Auxiliary Microcontroller (MCU) ===
[[Image:CTR_UC.png|600px]]
[[Image:CTR_UC.png|600px]]
Monitors HOME button, WiFi switch, 3D slider, volume control slider.
Monitors HOME button, WiFi switch, 3D slider, volume control slider.
Controls LEDs, various power supplies.
Controls LEDs, various power supplies via an I²C connection to the PMIC.
Devices attached to I2C bus:
Two I²C buses are attached to the MCU. For one, the SoC is the master; for the other, the MCU is the master.
* UC (master?)
Devices attached to MCU master I²C bus:
* MCU (master)
* Fuel Gauge
* Accelerometer (slave address 0x18)
* Accelerometer (slave address 0x18)
* SoC (master? slave?)
* PMIC
* maybe more?
Devices attached to the SoC master I²C bus:
* SoC (master)
* MCU
* LCD
* Camera
* QTM (New3DS-only)
The MCU uses the [http://mcs.uwsuper.edu/sb/327/Resources/RL78.pdf RL78 ISA].
The MCU uses some custom Special Function Registers, but documentation for much of the hardware protocol/general SFRs can be found [http://courses.ee.sun.ac.za/Computer_Systems_245/Dokumentasie/RL78%20hardware%20manual%20(registers).pdf here].