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Line 22: − The above clock-rates were calculated by calling svcGetSystemTick in sets of 5(call it, execute svcSleepThread for 1s, then call it again), then the average of those were calculated. The clock-rate listed above applies for *all* 4 New3DS MPCores. This is referring to the "~268123480 Hz" clock-rate.+ − − Line 32:
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→Specifications: even copy and paste has its problems
! Type !! Description
! Type !! Description
|-
|-
| ARM11 Processor Core || Old3DS: [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/index.html ARM11 2x MPCore & 2x VFPv2 Co-Processor] 268MHz(~268123480 Hz).
| ARM11 Processor Core || Old3DS: [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/index.html ARM11 2x MPCore & 2x VFPv2 Co-Processor] 268MHz (268,111,856.0 ± 2<sup>-32</sup> Hz, i.e. exactly twice the clock rate of the ARM9).
New3DS: 4x MPCore, 4x VFPv2, able to run up to 804MHz (see below). It also has an optional 2MB L2 cache.
New3DS: 4x MPCore, 4x VFPv2, able to run up to 804MHz (see below). It also has an optional 2MB L2 cache.
|-
|-
| ARM9 Processor Core || [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0201d/index.html ARM946] 134MHz(~134058675 Hz),
| ARM9 Processor Core || [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0201d/index.html ARM946] 134MHz (134,055,927.9 ± 2<sup>-32</sup> Hz),
|-
|-
| GPU || [http://en.wikipedia.org/wiki/PICA200 DMP PICA] 268MHz,
| GPU || [http://en.wikipedia.org/wiki/PICA200 DMP PICA] 268MHz,
|}
|}
New3DS exclusives are able to clock the CPU at 804MHz, but this appears to be limited to the currently running application/app cores. Timed by running svcGetSystemTick on either side of a long idle loop to stay in the current process context. svcGetSystemTick uses a tick counter running at 268MHz in this mode.
New3DS exclusives are able to clock the CPU at 804MHz, but this appears to be limited to the currently running application/app cores. Timed by running svcGetSystemTick on either side of a long idle loop to stay in the current process context. svcSleepThread + svcGetSystemTick implies a tick counter running at 268MHz in this mode.
On New3DS: when Home Menu is active, the system runs at 804MHz. For everything else, it's 268MHz, except when the app(let) has the required flag set. See [[NCCH/Extended_Header|here]] and [[PDN_Registers|here]] for details, regarding clock-rate and cache.
On New3DS: when Home Menu is active, the system runs at 804MHz. For everything else, it's 268MHz, except when the app(let) has the required flag set. See [[NCCH/Extended_Header|here]] and [[PDN_Registers|here]] for details, regarding clock-rate and cache.
== Specifications ==
== Specifications ==
{| class="wikitable"
{| class="wikitable"
! Type !! 3DS !! 3DSXL !! 2DS !! N3DS !! N3DSXL
! Type !! 3DS !! 3DSXL !! 2DS !! N3DS !! N3DSXL !! N2DSXL
|-
| Model || CTR-001 || SPR-001 || || KTR-001 || || JAN-001
|-
|-
| SoC || CPU CTR (1048 0H)
| SoC || CPU CTR (1048 0H)
|| CPU CTR A (1226 60)
|| CPU CTR A (1226 60)
CPU CTR (1037 21)
CPU CTR (1037 21)
|| CPU CTR B (??) || CPU LGR A (1444 86) || CPU LGR A (1446 17)
|| CPU CTR B (??) || CPU LGR A (1444 86) || CPU LGR A (1446 17) || ??
|-
|-
| FCRAM || [http://www.fujitsu.com/downloads/MICRO/fma/pdf/MB81EDS516545_e511463.pdf 2x64MB Fujitsu MB82M8080-07L] || Fujitsu MB82DBS16641 || Fujitsu MB82DBS1664 || ?? || Fujitsu MB82MK9A9A
| FCRAM || [http://www.fujitsu.com/downloads/MICRO/fma/pdf/MB81EDS516545_e511463.pdf 2x64MB Fujitsu MB82M8080-07L] || Fujitsu MB82DBS16641 || Fujitsu MB82DBS1664 || ?? || Fujitsu MB82MK9A9A || ??
|-
|-
| Top Screen || 3.53 in, 3D || 4.88 in, 3D || 3.53 in(?) cropped from a single panel || 3.88 in, 3D || 4.88 in, 3D
| Top Screen || 3.53 in, 3D || 4.88 in, 3D || 3.53 in cropped from a single panel || 3.88 in, 3D || 4.88 in, 3D || 4.88 in (?)
|-
|-
| Bottom Screen || 3.00 in || 4.18 in || 3.00 in(?) cropped from a single panel || 3.33 in || 4.18 in
| Bottom Screen || 3.00 in || 4.18 in || 3.00 in cropped from a single panel || 3.33 in || 4.18 in || 4.18 in (?)
|-
|-
| Storage ||colspan="3"| Toshiba THGBM2G3P1FBAI8 1GB ||colspan="2"| Samsung KLM4G1YEQC 4GB (in 1.3GiB SLC mode)
| Storage ||colspan="2"| Toshiba THGBM2G3P1FBAI8 1GB ||colspan="1"| Changed between O3DS and N3DS parts depending on production date ||colspan="2"| Samsung KLM4G1YEQC 4GB (in 1.3GiB SLC mode) or Toshiba THGBMBG4P1KBAIT 2GB (MLC, approx. 1.8GiB usable) ||colspan="1"| ??
Toshiba THGBMBG4P1KBAIT 2GB (MLC, approx. 1.8GiB usable)
|-
|-
| Audio Codec || TI PAIC3010B 0AA37DW || ?? || ?? || TI AIC3010B 39C4ETW || TI AIC3010D 48C01JW
| Speaker, Microphone, Circlepad, Touch controller || TI PAIC3010B 0AA37DW || ?? || ?? || TI AIC3010B 39C4ETW || TI AIC3010D 48C01JW || ??
|-
|-
| Gyroscope || [http://dl-web.dropbox.com/u/20520664/references/PS-ITG-3200-00-01.4.pdf Invensense ITG-3270 MEMS Gyroscope] || ?? || ?? || ?? || ??
| Gyroscope || [http://dl-web.dropbox.com/u/20520664/references/PS-ITG-3200-00-01.4.pdf Invensense ITG-3270 MEMS Gyroscope] || ?? || ?? || ?? || ?? || ??
|-
|-
| Accelerometer || ST Micro 2048 33DH X1MAQ Accelerometer Model LIS331DH || ?? || ?? || ?? || ??
| Accelerometer || ST Micro 2048 33DH X1MAQ Accelerometer Model LIS331DH || ?? || ?? || ?? || ?? || ??
|-
|-
| Wifi || Atheros AR6014 || ?? || ?? || ?? || Atheros AR6014G-AL1C
| Wifi || Atheros AR6014 || ?? || ?? || ?? || Atheros AR6014G-AL1C || ??
|-
|-
| Infrared IC || NXP S750 0803 TSD031C || ?? || ?? || ?? || NXP S750 1603 TSD438C
| Infrared IC || NXP S750 0803 TSD031C || ?? || ?? || ?? || NXP S750 1603 TSD438C || ??
|-
|-
| Custom Microcontroller || Renesas UC CTR || ?? || Renesas UC CTR 324KM47 KG10 || Renesas UC KTR || Renesas UC KTR 442KM13 TK14
| Custom Microcontroller || Renesas UC CTR || ?? || Renesas UC CTR 324KM47 KG10 || Renesas UC KTR || Renesas UC KTR 442KM13 TK14 || ??
|-
|-
| PMIC? || TI 93045A4 OAAH86W || ?? || ?? || TI 93045A4 38A6TYW G2 || TI 93045A4 49AF3NW G2
| PMIC? || TI 93045A4 OAAH86W || ?? || ?? || TI 93045A4 38A6TYW G2 || TI 93045A4 49AF3NW G2 || ??
|-
| Wifi SPI Flash
| Raw ID data: 20 58 || ?? || ?? || Raw ID data: 62 62 || ?? || ??
|}
|}
* [12] This IC is somewhat similar to [http://www.alldatasheet.net/datasheet-pdf/pdf/347838/NXP/SC16IS750IBS.html this].
* [12] This IC is somewhat similar to [http://www.alldatasheet.net/datasheet-pdf/pdf/347838/NXP/SC16IS750IBS.html this].
* The Raw ID data for Wifi SPI Flash is from command 0x9F, RDID.
== FCRAM ==
== FCRAM ==
Nintendo recommends SD cards up to 32 GB however the internal SDIO controller seems to support SD cards up to 2.19 Terabyte (32-bit sector number). It's unknown if it really can handle that much. 128 GB was tested and works fine however it causes a major slowdown of the system especially at boot.
Nintendo recommends SD cards up to 32 GB however the internal SDIO controller seems to support SD cards up to 2.19 Terabyte (32-bit sector number). It's unknown if it really can handle that much. 128 GB was tested and works fine however it causes a major slowdown of the system especially at boot.
== Images ==
== Images ==
This is the interface for the 'NEW' WiFi module (based on Atheros AR6002) first included in DSi.
This is the interface for the 'NEW' WiFi module (based on Atheros AR6002) first included in DSi.
The proprietary and by now ancient DS-mode WiFi is colored yellow, pins are unknown.
The proprietary DS-mode WiFi is colored yellow, pins are unknown.
I²C eeprom is colored blue:
* SCL
* SCL
* SDA
* SDA
* NC
* NC
=== Auxiliary Microcontroller ===
=== Auxiliary Microcontroller (MCU) ===
[[Image:CTR_UC.png|600px]]
[[Image:CTR_UC.png|600px]]
Monitors HOME button, WiFi switch, 3D slider, volume control slider.
Monitors HOME button, WiFi switch, 3D slider, volume control slider.
Controls LEDs, various power supplies.
Controls LEDs, various power supplies via an I²C connection to the PMIC.
Devices attached to I2C bus:
Two I²C buses are attached to the MCU. For one, the SoC is the master; for the other, the MCU is the master.
* UC (master?)
Devices attached to MCU master I²C bus:
* MCU (master)
* Fuel Gauge
* Accelerometer (slave address 0x18)
* Accelerometer (slave address 0x18)
* SoC (master? slave?)
* PMIC
* maybe more?
Devices attached to the SoC master I²C bus:
* SoC (master)
* MCU
* LCD
* Camera
* QTM (New3DS-only)
The MCU uses the [http://mcs.uwsuper.edu/sb/327/Resources/RL78.pdf RL78 ISA].
The MCU uses some custom Special Function Registers, but documentation for much of the hardware protocol/general SFRs can be found [http://courses.ee.sun.ac.za/Computer_Systems_245/Dokumentasie/RL78%20hardware%20manual%20(registers).pdf here].