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Line 693: − + − + − + − − Reading from this register seem to read N bytes from the bank while incrementing the internal index by the same amount. Line 682:
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Added info on DebugPad
| 0xa6
| 0xa6
| "i2c::HID"
| "i2c::HID"
| Debug(?) gyroscope. The device table in I2C-module had the device address changed from 0xA6 to 0xD6 with [[8.0.0-18]].
| Gyroscope. The device table in I2C-module had the device address changed from 0xA6 to 0xD6 with [[8.0.0-18]].
|-
|-
| 10
| 10
| 0xa4
| 0xa4
| "i2c::HID"
| "i2c::HID"
| DebugPad
| DebugPad (slightly modified [https://wiibrew.org/wiki/Wiimote/Extension_Controllers/Classic_Controller_Pro Wii Classic Controller Pro])
|-
|-
| 13
| 13
s* = shared register (explaination below this table)
s* = shared register (explaination below this table)
ds = dynamic shared (explaination below this table)
ds = dynamic shared (explaination below this table)
Reading or writing multiple bytes from/to single-byte registers increments the register ID along with it. For example reading two bytes from reg 0x00 reads regs 0x00 and 0x01.
This is not the case for multibyte regs (0x29, 0x2D, 0x4F, 0x61 and 0x7F), plus reg 0x60.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! REGISTER
! REGISTER
| d
| d
| rw
| rw
| 2bit value, writing will mask away/"acknowledge" the event, set to 3 by mcuMainLoop on reset if reset source is Watchdog
| For bit0 and 1 values, writing will mask away/"acknowledge" the event, set to 3 by mcuMainLoop on reset if reset source is Watchdog
bit0: RTC clock value got reset to defaults
bit0: RTC clock value got reset to defaults
bit1: Watchdog reset happened
bit1: Watchdog reset happened
bit5: TWL MCU reg: volume mode (0: 8-step, 1: 32-step)
bit6: TWL MCU reg: NTR (0) vs TWL mode (1)
bit7: TWL MCU reg: Uses NAND
|-
|-
| 0x03
| 0x03
| s
| s
| ro
| ro
| ? (seems to be power management related?)
| Battery temperature (in Celcius?)
|-
|-
| 0x0B
| 0x0B
| s
| s
| ro
| ro
| ? (changes to 0 for a second when the charger is plugged in then it resets to its previous value)
| Battery percentage, fractional part (seems to have a resolution of around 0.1% according to tests)
|-
|-
| 0x0D
| 0x0D
| System power control:
| System power control:
bit0: power off
bit0: power off
bit1: reboot (unused?)
bit1: full reboot (unused). Discards things like [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]]
bit2: reboot (used by mcu sysmodule and LgyBg)
- Asserts RESET1 via PMIC command (?) (deasserts nRESET1). This could be the reset that controls some CFG9 registers
bit3: used by LgyBg to power off, causes hangs in 3DS-mode
- Asserts RESET2 (P0.1 = 0, PM0.1 = 0 (output)) (deasserts nRESET2)
bit4: used by PTM to signal that sleep mode is about to be entered
- Asserts FCRAM_RESET (P3.0 = 0) (deasserts nFCRAM_RESET)
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
bit2: normal reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.
- Asserts RESET2 (P0.1 = 0, PM0.1 = 0)
- If in NTR emulation mode (see reg 0x02), asserts FCRAM_RESET (P3.0 = 0)
- Resets TWL MCU i2c registers
bit3: FCRAM reset (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also possibly implements this function)
- Asserts FCRAM_RESET (P3.0 = 0)
bit4: signal that sleep mode is about to be entered (used by PTM)
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
If any of the reset bits is set, the MCU waits for 5ms, then deasserts RESET1 (via PMIC), RESET2 (PM0.1 = 1 (input)) and FCRAM_RESET (P3.0 = 1), and reinitializes some other various registers after a 100ms delay.
|-
|-
| 0x21
| 0x21
| d
| d
| wo
| wo
| ??? switches up input bits from <code>0123456--</code> to <code>12-0435-</code> then writes them to REG[0x5D] (<code>0xFFC02</code>)
| Used in legacy mode to signal events for TWL MCU "emulation" (written to REG[0x5D])? Software then asserts the TWL MCU IRQ pin via [[#LGY_GPIOEMU_MASK|Legacy I/O registers]].
bit0: Signal TWL POWER button click
bit1: Signal TWL reset
bit2: Signal TWL power off
bit3: Signal TWL battery low
bit4: Signal TWL battery empty
bit5: Signal TWL volume button click
|-
|-
| 0x22
| 0x22
| d
| d
| wo
| wo
| Writing 0x72 ('r') resets the MCU, writing 0x77 ('w') resets its WDT. Seems to require special conditions, or doesn't work on current units
| Writing 0x72 ('r') resets the MCU, but this is stubbed on retail?
|-
|-
| 0x24
| 0x24
| 0x29
| 0x29
| sd(5)
| sd(5)
| ??
| rw
| Power mode indicator state (read-write)
| Power mode indicator state (read-write)
1 = forced default blue
1 = forced default blue
| s
| s
| rw
| rw
| Could be used on very old MCU_FIRM versions to upload [[MCU_Services#MCU_firmware_versions|MCU firmware]] if some conditions are met.
| Could be used on extremely old MCU_FIRM versions to upload [[MCU_Services#MCU_firmware_versions|MCU firmware]] if reg 0xF == 0 and reg 0x10 == 1 (presumably major and minor version fields for mcufw 0.1 which largely predates factory firm).
|-
|-
| 0x3D
| 0x3D
|-
|-
| 0x3F
| 0x3F
| s
| d
| wo
| wo
| 2 bits
| 2 bits
bit0: turns off P00 and sets it to output mode (seems to kill the entire SoC)
bit0: Asserts RESET1 (P0.0 = 0, PM0.0 = 0 (output)) but does NOT deassert it (wtf?). This seems to kill the entire SoC: is it because it doesn't deassert it, or does it not deassert it because the SoC hangs anyway? This is the pin that controls some security-critical regs like CFG9_BOOTENV!
bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
|-
|-
|-
|-
| 0x60
| 0x60
| ds
| d
| rw
| rw
| Free register bank address select
| Free register bank address (index) select
Selects the index to read from in the free register bank, up to 200 (?). Used with reg 0x61.
Selects the index to read from in the free register bank, up to 200. Used in conjunction with reg 0x61.
byte 0: bit0 = "WirelessDisabled", bit1 = "SoftwareClosed", bit2 = "PowerOffInitiated", bit3 = "LgyNativeResolution", bit4 = "LegacyJumpProhibited"
byte 0: bit0 = "WirelessDisabled", bit1 = "SoftwareClosed", bit2 = "PowerOffInitiated", bit3 = "LgyNativeResolution", bit4 = "LegacyJumpProhibited"
bytes 4 and 5: UUID clock sequence
bytes 4 and 5: UUID clock sequence
bytes 6 and 7: Unused
bytes 6 and 7: Unused
bytes 8 to 175: Play count data for legacy titles
bytes 8 to 175: Playtime data for legacy titles
bytes 176 to 199: Unused
bytes 176 to 188: Playtime data
bytes 188 to 199: Unused
|-
|-
| 0x61
| 0x61
| ds(0x100)
| d(200)
| rw
| rw
| Free register bank, data is read from/written to here.
| Free register bank, data is read from/written to here.
Accessing N bytes of this register increments the selected index by N.
|-
|-
| 0x62 - 0x7E
| 0x62 - 0x7E
| ro
| ro
| Various system state information (debug pointer table)
| Various system state information (debug pointer table)
byte 0x00: Console type, see [[Configuration_Memory#MCU_HW_INFO|here]]
byte 0x01: PMIC vendor code
byte 0x02: Battery vendor code
byte 0x03: MGIC version (major?)
byte 0x04: MGIC version (minor?)
byte 0x05: RCOMP(?)
byte 0x06: battery related? (seems to decrease while charging and increase while discharging)
byte 0x06: battery related? (seems to decrease while charging and increase while discharging)
byte 0x09: system model (see [[Cfg:GetSystemModel#System_Model_Values|Cfg:GetSystemModel]] for values)
byte 0x09: system model (see [[Cfg:GetSystemModel#System_Model_Values|Cfg:GetSystemModel]] for values)
|}
|}
This is the DebugPad device, see [[HID_Shared_Memory|here]].
This is a [https://wiibrew.org/wiki/Wiimote/Extension_Controllers/Classic_Controller_Pro Wii Classic Controller Pro] which was slightly modified to have an encrypted device type of 0xF0 [https://wiibrew.org/wiki/Wiimote/Extension_Controllers#The_New_Way instead of 0xFD].
See [[HID_Shared_Memory#Offset_0x238|here]] for the HID shared memory report format.
== Device 13 ==
== Device 13 ==