215
edits
Changes
Update MTX bits and interrupts
|-
|-
| 0x1EC1x00C
| 0x1EC1x00C
| ???
| [[#MTX_IE|MTX_IE]]
| 4
| 4
|-
|-
==Matrix unit==
==Matrix unit==
There are two matrix units, one at +0x200, and the other one at +0x300, possibly one for each axis (X and Y)
There are two matrix units, one at +0x200 for vertical (Y) scaling, and the other one at +0x300 for horizontal (X) scaling.
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{| class="wikitable" border="1"
|-
|-
| 1
| 1
| ??? set after init sequence
| Enable vertical matrix
|-
|-
| 2
| 2
| ??? set after init sequence
| Enable horizontal matrix
|-
|-
| 3
| 4
| ???
| ???
|-
|-
| 4
| 5
| ???
| ???
|-
|-
|-
|-
| 10-11
| 10-11
| Output pixel mode? Same enum as above.
| Output framebuffer rotation: 0 = normal, 1 = 90° CW (right), 2 = 180° CW (upside down, not mirrored), 3 = 270° CW (left)
|-
|-
| 12
| 12
| ??? initialized to 0, but if set then requires the output width and height to be multiples of 8
| Output tiling for use with the GPU. When set, the output width and height must be a multiple of 8.
|-
|-
| 15
| 15
| ??? set after init sequence
| Start bit (setting this will eventually raise MTX interrupt 0)
|-
|-
| 16
| 16
| ??? not yet inited bit ???
| Data still available flag (?)
|-
|-
|}
|}
|-
|-
| 0-8
| 0-8
| Output framebuffer width - 1 is written here
| Output framebuffer width - 1 is written here, 1 <= width <= 512
|-
|-
| 16-25
| 16-25
| Output framebuffer height - 1 is written here
| Output framebuffer height - 1 is written here, 1 <= height <= 512
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|-
|}
|}
Reading this register will return pending interrupts.
Reading this register will return pending interrupts.
Writing this register will acknowledge the pending interrupt.
Writing this register will acknowledge pending interrupts where the bits are set.
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{| class="wikitable" border="1"
|-
|-
| 0
| 0
| Interrupt 0
| FIFO ready (signal to start DMA)
|-
|-
| 1
| 1
| Interrupt 1
| FIFO overrun(?) (occurs if DMA is too slow)
|-
|-
| 2
| 2
| Interrupt 2
| FIFO underrun(?) (occurs on VBlank)
|-
|-
|}
|}
==MTX_IE==
Interrupt Enable for the above interrupts.