6,263
edits
Changes
Jump to navigation
Jump to search
Line 70:
Line 70: − +
→0x17E10000
==0x17E10000==
==0x17E10000==
The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero.
The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. Therefore: bit0 set = new cache hardware enabled, clear = new cache hardware disabled.
=ARM9 Physical memory regions =
=ARM9 Physical memory regions =