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→0x17E10000
==0x17E10000==
==0x17E10000==
The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. Therefore: bit0 set = new cache hardware enabled, clear = new cache hardware disabled.
The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. Therefore: bit0 set = new cache hardware enabled, clear = new cache hardware disabled(this bit is how the ARM11-kernel checks whether the additional cache hw is enabled).
To enable the additional cache hw, the following is used by the ARM11-kernel:
* Sets bit0 in 32bit register 0x17E10000+0x100.
To disable the additional cache hw, the following is used by the ARM11-kernel:
* Writes value 0xFFFF to 32bit register 0x17E10000+0x77C.
* Waits for bit0 in 32bit register 0x17E10000+0x730 to become clear.
* Writes value 0x0 to 32bit register 0x17E10000+0x0.
* Clears bit0 in 32bit register 0x17E10000+0x100.
=ARM9 Physical memory regions =
=ARM9 Physical memory regions =