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→Startup modes (27-24)
3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem.
3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the ARM9 bootrom, including the protected part before it is locked out.
= Registers =
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Old3DS
! Old3DS
| 0x10002000
| 0x10002000
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10002004 + (n*0x1c)
| 0x10002004 + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10002008 + (n*0x1c)
| 0x10002008 + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x1000200c + (n*0x1c)
| 0x1000200c + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10002010 + (n*0x1c)
| 0x10002010 + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10002014 + (n*0x1c)
| 0x10002014 + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10002018 + (n*0x1c)
| 0x10002018 + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x1000201C + (n*0x1c)
| 0x1000201C + (n*0x1c)
| 4
| 4
|
| Boot9, Kernel9
|}
|}
== NDMA_GLOBAL_CNT ==
== NDMA_GLOBAL_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
| 0
| Global enable?
|-
|-
| 19-16
| 19-16
== NDMA_SRC_ADDR ==
== NDMA_SRC_ADDR ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 31-0
| 31-0
== NDMA_TRANSFER_CNT ==
== NDMA_TRANSFER_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 27-0
| 27-0
== NDMA_WRITE_CNT ==
== NDMA_WRITE_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 23-0
| 23-0
== NDMA_BLOCK_CNT ==
== NDMA_BLOCK_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 15-0
| 15-0
== NDMA_FILL_DATA ==
== NDMA_FILL_DATA ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 31-0
| 31-0
== NDMA_CNT ==
== NDMA_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 11-10
| 11-10
| Enable/busy flag.
| Enable/busy flag.
|}
|}
== Startup modes (27-24) ==
== Startup modes (27-24) ==
???
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| TIMER0
|-
| 1
| TIMER1
|-
| 2
| TIMER2
|-
| 3
| TIMER3
|-
| 4
| CTRCARD0
|-
| 5
| CTRCARD1
|-
| 6
| MMC1
|-
| 7
| MMC2?
|-
| 8
| AES in ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO|WRFIFO]])
|-
| 9
| AES out ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO|RDFIFO]])
|-
| 10
| SHA in ([[SHA_Registers#SHA_FIFO|INFIFO]])
|-
| 11
| SHA out ([[SHA_Registers#SHA_FIFO|INFIFO]])
|-
| 12
| ?
|-
| 13
| ?
|-
| 14
| ?
|-
| 15
| Boot9 Uses this to copy from the AES out FIFO to the SHA in FIFO
|}
== Block transfers ==
== Block transfers ==