516
edits
Changes
Jump to navigation
Jump to search
Line 1:
Line 1: − + − == Registers ==+ − + − + − + + + − + + + − + + + − + + + − + + + − + + + − + + + − + + + − + + + − + − + − + + + + Line 52:
Line 73: − + − + − + − + − + Line 70:
Line 91: − + − + − + − + Line 81:
Line 102: − + − + − + Line 90:
Line 111: − + − + − + Line 102:
Line 123: − + − + − + Line 111:
Line 132: − + − + − + + + + Line 147:
Line 171: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + − + − ???+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + − + − + − + − + − +
Add device to device modes
3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem.
3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. NDMA can access the Arm9 bootrom, including the protected part before it is locked out.
= Registers =
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! NAME
! Old3DS
! ADDRESS
! Name
! WIDTH
! Address
! Width
! Used by
|-
|-
| REG_NDMAGCNT
| style="background: green" | Yes
| [[#NDMA_GLOBAL_CNT|NDMA_GLOBAL_CNT]]
| 0x10002000
| 0x10002000
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMASAD(n)
| style="background: green" | Yes
| [[#NDMA_SRC_ADDR|NDMA_SRC_ADDR]](n)
| 0x10002004 + (n*0x1c)
| 0x10002004 + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMADAD(n)
| style="background: green" | Yes
| [[#NDMA_DST_ADDR|NDMA_DST_ADDR]](n)
| 0x10002008 + (n*0x1c)
| 0x10002008 + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMATCNT(n)
| style="background: green" | Yes
| [[#NDMA_TRANSFER_CNT|NDMA_TRANSFER_CNT]](n)
| 0x1000200c + (n*0x1c)
| 0x1000200c + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMAWCNT(n)
| style="background: green" | Yes
| [[#NDMA_WRITE_CNT|NDMA_WRITE_CNT]](n)
| 0x10002010 + (n*0x1c)
| 0x10002010 + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMABCNT(n)
| style="background: green" | Yes
| [[#NDMA_BLOCK_CNT|NDMA_BLOCK_CNT]](n)
| 0x10002014 + (n*0x1c)
| 0x10002014 + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMAFDATA(n)
| style="background: green" | Yes
| [[#NDMA_FILL_DATA|NDMA_FILL_DATA]](n)
| 0x10002018 + (n*0x1c)
| 0x10002018 + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|-
|-
| REG_NDMACNT(n)
| style="background: green" | Yes
| [[#NDMA_CNT|NDMA_CNT]](n)
| 0x1000201C + (n*0x1c)
| 0x1000201C + (n*0x1c)
| 4
| 4
| Boot9, Kernel9
|}
|}
== REG_NDMAGCNT ==
== NDMA_GLOBAL_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
| 0
| Global enable?
|-
|-
| 19-16
| 19-16
|}
|}
== REG_NDMASAD ==
== NDMA_SRC_ADDR ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 31-0
| 31-0
| Source data address. Must be multiple of 4.
| Source data address. Must be multiple of 4.
|}
|}
Like old DMA, REG_NDMASAD is copied to internal registers when written to.
Like old DMA, NDMA_SRC_ADDR is copied to internal registers when written to.
== REG_NDMADAD ==
== NDMA_DST_ADDR ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! BIT
| Destination data address. Must be multiple of 4.
| Destination data address. Must be multiple of 4.
|}
|}
Like old DMA, REG_NDMADAD is copied to internal registers when written to.
Like old DMA, NDMA_DST_ADDR is copied to internal registers when written to.
== REG_NDMATCNT ==
== NDMA_TRANSFER_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 27-0
| 27-0
|}
|}
== REG_NDMAWCNT ==
== NDMA_WRITE_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 23-0
| 23-0
|}
|}
== REG_NDMABCNT ==
== NDMA_BLOCK_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 15-0
| 15-0
|}
|}
== REG_NDMAFDATA ==
== NDMA_FILL_DATA ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
|-
| 31-0
| 31-0
|}
|}
== REG_NDMACNT ==
== NDMA_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! BIT
! Bit
! DESCRIPTION
! Description
|-
| 4-0
| Device to device startup mode
|-
|-
| 11-10
| 11-10
|}
|}
== Startup modes (4-0) ==
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| TIMER0
|-
| 1
| TIMER1
|-
| 2
| TIMER2
|-
| 3
| TIMER3
|-
| 4
| CTRCARD0
|-
| 5
| CTRCARD1
|-
| 6
| SDIO1
|-
| 7
| SDIO3
|-
| 8
| AES in ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO|WRFIFO]])
|-
| 9
| AES out ([[AES_Registers#AES_WRFIFO.2FAES_RDFIFO|RDFIFO]])
|-
| 10
| SHA in ([[SHA_Registers#SHA_FIFO|INFIFO]])
|-
| 11
| SHA out ([[SHA_Registers#SHA_FIFO|INFIFO]], source data readback mode)
|-
| 12
| NTRCARD
|-
| 13
| ?
|-
| 14
| ?
|-
| 15
| Device to device (subclassed by bits 4-0)
|}
== Startup modes (27-24) ==
== Device to device startup modes (4-0) ==
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| CTRCARD0 -> AES
|-
| 1
| CTRCARD1 -> AES
|-
| 2
| AES -> CTRCARD0
|-
| 3
| AES -> CTRCARD1
|-
| 4
| CTRCARD0 -> SHA
|-
| 5
| CTRCARD1 -> SHA
|-
| 6
| SHA -> CTRCARD0
|-
| 7
| SHA -> CTRCARD1
|-
| 8
| SDIO1 -> AES
|-
| 9
| SDIO3 -> AES
|-
| 10
| AES -> SDIO1
|-
| 11
| AES -> SDIO3
|-
| 12
| SDIO1 -> SHA
|-
| 13
| SDIO3 -> SHA
|-
| 14
| SHA -> SDIO1
|-
| 15
| SHA -> SDIO3
|-
| 16
| AES -> SHA
|-
| 17
| SHA -> AES
|}
== Block transfers ==
== Block transfers ==
First, a word is always 32 bits. Second, the block transfer specified in REG_NDMACNT is the smallest atom of data that will be transferred in a burst. The bus is monopolized until this block is transferred, without splitting up.
First, a word is always 32 bits. Second, the block transfer specified in NDMA_CNT is the smallest atom of data that will be transferred in a burst. The bus is monopolized until this block is transferred, without splitting up.
The next block transfer will happen after the specified time in the REG_NDMABCNT interval timer, until done.
The next block transfer will happen after the specified time in the NDMA_BLOCK_CNT interval timer, until done.
== Immediate mode ==
== Immediate mode ==
Transfers the words specified in REG_NDMAWCNT immediately following block transfer rules. REG_NDMATCNT and repeating mode are ignored.
Transfers the words specified in NDMA_WRITE_CNT immediately following block transfer rules. NDMA_TRANSFER_CNT and repeating mode are ignored.
== Repeating mode ==
== Repeating mode ==
Transfers the words specified in REG_NDMAWCNT following the startup mode event. REG_DMATCNT is ignored.
Transfers the words specified in NDMA_WRITE_CNT following the startup mode event. NDMA_TRANSFER_CNT is ignored.
== No immediate and no repeating mode ==
== No immediate and no repeating mode ==
Transfers the words specified in REG_NDMAWCNT for each startup event, and gets disabled when the total number of words in REG_NDMATCNT are transferred.
Transfers the words specified in NDMA_WRITE_CNT for each startup event, and gets disabled when the total number of words in NDMA_TRANSFER_CNT are transferred.