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Changes

PDN Registers (edit)

Revision as of 18:43, 19 January 2021

117 bytes removed ,  18:43, 19 January 2021
Small cleanup
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#PDN_CNT|PDN_CNT]]
+
| [[#PDN_SLEEP_CNT|PDN_SLEEP_CNT]]
 
| 0x10141000
 
| 0x10141000
 
| 2
 
| 2
−
| Kernel11, TwlBg
+
| Kernel11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
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|-style="border-top: double"
 
|-style="border-top: double"
 
| style="background: red" | No
 
| style="background: red" | No
−
| [[#PDN_MPCORE_SOCMODE|PDN_MPCORE_SOCMODE]]
+
| [[#PDN_LGR_SOCMODE|PDN_LGR_SOCMODE]]
 
| 0x10141300
 
| 0x10141300
 
| 2
 
| 2
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|-
 
|-
 
| style="background: red" | No
 
| style="background: red" | No
−
| [[#PDN_MPCORE_CNT|PDN_MPCORE_CNT]]
+
| [[#PDN_LGR_CNT|PDN_LGR_CNT]]
 
| 0x10141304
 
| 0x10141304
 
| 2
 
| 2
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|-
 
|-
 
| style="background: red" | No
 
| style="background: red" | No
−
| [[#PDN_MPCORE_BOOTCNT<0-3>|PDN_MPCORE_BOOTCNT]]<0-3>
+
| [[#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3>
 
| 0x10141310
 
| 0x10141310
 
| 1*4
 
| 1*4
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|}
 
|}
   −
==PDN_CNT==
+
==PDN_SLEEP_CNT==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
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|-
 
|-
 
| 15
 
| 15
−
| 1 = VRAM is in self-refresh mode
+
| 1 = VRAM is powered down
 
|}
 
|}
   −
Kernel11 puts VRAM in self-refresh mode (before going to sleep) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally polls this register.
+
Kernel11 powers down VRAM (it's unclear whether bit15 is power-down or self-refresh mode) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally writes to and polls this register.
    
==PDN_WAKE_ENABLE==
 
==PDN_WAKE_ENABLE==
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For each bit, write 1 to acknowledge, and 0 to clear (?).
 
For each bit, write 1 to acknowledge, and 0 to clear (?).
−
  −
==PDN_WIFICNT==
  −
{| class="wikitable" border="1"
  −
!  Old3DS
  −
!  Bits
  −
!  Description
  −
|-
  −
| style="background: green" | Yes
  −
| 0
  −
| Enable wifi subsystem
  −
|}
      
==LGY_MODE==
 
==LGY_MODE==
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PDN services holds reset for 0x30 Arm11 cycles.
 
PDN services holds reset for 0x30 Arm11 cycles.
   −
== PDN_MPCORE_SOCMODE ==
+
== PDN_LGR_SOCMODE ==
 
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
 
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
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* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
 
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
   −
== PDN_MPCORE_CNT ==
+
== PDN_LGR_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
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|}
 
|}
   −
Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] is set otherwise 1.
+
Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] (LGR2 supported) is set otherwise 1.
   −
== PDN_MPCORE_BOOTCNT<0-3> ==
+
== PDN_LGR_CPU_CNT<0-3> ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
TuxSH
516

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