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PDN Registers (edit)

Revision as of 02:32, 27 January 2021

12,291 bytes added ,  02:32, 27 January 2021
m
→‎PDN_LGR_CPU_CNT
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#REDIRECT [[CONFIG11 Registers]]
+
=Register table=
 +
{| class="wikitable" border="1"
 +
!  Old3DS
 +
!  Name
 +
!  Address
 +
!  Width
 +
!  Used by
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_SLEEP_CNT|PDN_SLEEP_CNT]]
 +
| 0x10141000
 +
| 2
 +
| Kernel11
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]]
 +
| 0x10141008
 +
| 4
 +
| [[PTM Services]], [[PDN Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_WAKE_REASON|PDN_WAKE_REASON]]
 +
| 0x1014100C
 +
| 4
 +
| [[PTM Services]], TwlBg, [[PDN Services]]
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 +
| [[#LGY_MODE|LGY_MODE]]
 +
| 0x10141100
 +
| 2
 +
| TwlProcess9, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_SLEEP_CNT|LGY_SLEEP_CNT]]
 +
| 0x10141104
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_IRQ_ENABLE|LGY_IRQ_ENABLE]]
 +
| 0x10141108
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_PAD_CNT|LGY_PAD_CNT]]
 +
| 0x1014110A
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_HIDEMU_MASK|LGY_HIDEMU_MASK]]
 +
| 0x10141110
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_HIDEMU_PAD|LGY_HIDEMU_PAD]]
 +
| 0x10141112
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_GPIOEMU_MASK|LGY_GPIOEMU_MASK]]
 +
| 0x10141114
 +
| 2
 +
| [[Codec Services]], TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_GPIOEMU_DATA|LGY_GPIOEMU_DATA]]
 +
| 0x10141116
 +
| 2
 +
| [[Codec Services]], TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_CARDDETECTEMU_MASK|LGY_CARDDETECTEMU_MASK]]
 +
| 0x10141118
 +
| 1
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_CARDDETECTEMU_DATA|LGY_CARDDETECTEMU_DATA]]
 +
| 0x10141119
 +
| 1
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| LGY_?
 +
| 0x10141120
 +
| 1
 +
| TwlBg
 +
|-
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 +
| [[#PDN_GPU_CNT|PDN_GPU_CNT]]
 +
| 0x10141200
 +
| 4
 +
| Boot11, Kernel11, [[PDN Services]], TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_VRAM_CNT|PDN_VRAM_CNT]]
 +
| 0x10141204
 +
| 1
 +
| Boot11, Kernel11, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_LCD_CNT|PDN_LCD_CNT]]
 +
| 0x10141208
 +
| 1
 +
| Boot11
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_FCRAM_CNT|PDN_FCRAM_CNT]]
 +
| 0x10141210
 +
| 2
 +
| Kernel11, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_I2S_CNT|PDN_I2S_CNT]]
 +
| 0x10141220
 +
| 1
 +
| Boot11, TwlBg, [[PDN Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_CAMERA_CNT|PDN_CAMERA_CNT]]
 +
| 0x10141224
 +
| 1
 +
| [[PDN Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_DSP_CNT|PDN_DSP_CNT]]
 +
| 0x10141230
 +
| 1
 +
| Process9, [[PDN Services]]
 +
|-
 +
| style="background: red" | No
 +
| [[#PDN_MVD_CNT|PDN_MVD_CNT]]
 +
| 0x10141240
 +
| 1
 +
|
 +
|-style="border-top: double"
 +
| style="background: red" | No
 +
| [[#PDN_LGR_SOCMODE|PDN_LGR_SOCMODE]]
 +
| 0x10141300
 +
| 2
 +
| NewKernel11
 +
|-
 +
| style="background: red" | No
 +
| [[#PDN_LGR_CNT|PDN_LGR_CNT]]
 +
| 0x10141304
 +
| 2
 +
| NewKernel11
 +
|-
 +
| style="background: red" | No
 +
| [[#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3>
 +
| 0x10141310
 +
| 1*4
 +
| NewKernel11
 +
|}
 +
 
 +
=Sleep registers=
 +
==PDN_SLEEP_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| 1 = Enter sleep mode
 +
|-
 +
| 2-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = VRAM is powered down
 +
|}
 +
 
 +
Kernel11 powers down VRAM (it's unclear whether bit15 is power-down or self-refresh mode) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally writes to and polls this register.
 +
 
 +
==PDN_WAKE_ENABLE==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 1
 +
| [[HID_Registers#HID_PAD_CNT|HID_PAD_CNT]]
 +
|-
 +
| 3
 +
| Shell opened
 +
|-
 +
| 4
 +
| Headphones not plugged in
 +
|-
 +
| 8
 +
| WiFi (?)
 +
|-
 +
| 19
 +
| Shell GPIO (?)
 +
|-
 +
| 26
 +
| [[I2C_Registers#Device_3|MCU interrupt]]
 +
|-
 +
| 30
 +
| Touch screen pressed
 +
|-
 +
| 31
 +
| CTR gamecard inserted/removed
 +
|-
 +
|}
 +
List in progress.
 +
 
 +
This is a OR list of wake triggers that will wake up the console from sleep and raise IRQ 0x58.
 +
 
 +
==PDN_WAKE_REASON==
 +
Same layout as [[#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]].
 +
 
 +
This is a OR list of the wake triggers that actually woke up the console.
 +
 
 +
For each bit, write 1 to acknowledge, and 0 to clear (?).
 +
 
 +
=Legacy registers=
 +
==LGY_MODE==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| Read only legacy mode set on reg 0x10018000.
 +
|-
 +
| 2-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = enable legacy mode.
 +
|}
 +
To boot into DSi or GBA mode first set register 0x10018000 to the desired mode and setup LgyFb. Then disable FCRAM by clearing bit 0 in reg 0x10201000, writing 0 to PDN_FCRAM_CNT followed by 1 and waiting for bit 2 to clear.
 +
 
 +
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.
 +
 
 +
==LGY_SLEEP_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Write 1 to wakeup GBA mode.
 +
|-
 +
| 1
 +
| Sleep state/ack. 1 when GBA mode entered sleep. Write 1 to ack.
 +
|-
 +
| 2
 +
| ?
 +
|-
 +
| 3-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = IRQ enable (IRQ 0x59)
 +
|}
 +
When a GBA game enters sleep mode and bit 15 is 1, IRQ 0x59 fires and bit 1 is set. Bit 1 must be acknowledged/written together with bit 0 otherwise GBA mode wakes up from sleep early sometimes.
 +
 
 +
==LGY_IRQ_ENABLE==
 +
[[ARM11_Interrupts|Arm11 interrupt]] enable bits for legacy interrupts, same bit layout as the GPIOEMU regs below.
 +
 
 +
==LGY_PAD_CNT==
 +
Also named "KEYCNT" on certain other DS(i)/GBA documentations.
 +
The value of this register is copied to [[HID_Registers|HID_PAD_CNT]] when GBA mode enters sleep.
 +
 
 +
==LGY_HIDEMU_MASK==
 +
Set bits will use the corresponding values from [[#LGY_HIDEMU_PAD|LGY_HIDEMU_PAD]] instead of allowing the hardware to read it from [[HID_Registers#HID_PAD|HID_PAD]].
 +
 
 +
This is set to 0x1FFF (all buttons and the debug key) and [[#LGY_HIDEMU_PAD|LGY_HIDEMU_PAD]] is set to 0 when the "Close this software and return to HOME Menu?" dialog is shown to prevent the button presses from propagating to the DS/GBA CPU.
 +
 
 +
==LGY_HIDEMU_PAD==
 +
Works the same way as [[HID_Registers#HID_PAD|HID_PAD]], but the values set here are only replaced in the HID_PAD seen by the DS/GBA CPU when the corresponding bits in [[#LGY_HIDEMU_MASK|LGY_HIDEMU_MASK]] are set.
 +
 
 +
==LGY_GPIOEMU_MASK==
 +
Set bits will read bits from [[#LGY_GPIOEMU_DATA|LGY_GPIOEMU_DATA]] (override).
 +
 
 +
This is used to trigger things like the TWL MCU interrupt in TWL mode.
 +
 
 +
==LGY_GPIOEMU_DATA==
 +
See above
 +
 
 +
==LGY_CARDDETECTEMU_MASK==
 +
Set bits will read bits from [[#LGY_CARDDETECTEMU_DATA|LGY_CARDDETECTEMU_DATA]] (override).
 +
 
 +
Bit0 signals cartridge removal.
 +
 
 +
==LGY_CARDDETECTEMU_DATA==
 +
See above
 +
 
 +
=Clock and reset registers=
 +
==PDN_GPU_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| GPU main block + VRAM + LCD reset. 0 = reset.
 +
|-
 +
| 1
 +
| PSC block reset? 0 = reset.
 +
|-
 +
| 2
 +
| Geoshader block reset? 0 = reset.
 +
|-
 +
| 3
 +
| Rasterization block reset? 0 = reset.
 +
|-
 +
| 4
 +
| PPF block reset. 0 = reset.
 +
|-
 +
| 5
 +
| PDC block reset? 0 = reset.
 +
|-
 +
| 6
 +
| PDC related reset. 0 = reset.
 +
|-
 +
| 7-15
 +
| Unused.
 +
|-
 +
| 16
 +
| Clock enable for all blocks, VRAM and LCD. 1 = enable.
 +
|}
 +
 
 +
PDN uses a 12 ARM11 cycle delay to deassert reset.
 +
 
 +
==PDN_VRAM_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
This register seems to be unimplemented in released models: while it is used in tandem with PDN_GPU_CNT.bit16 in Boot11 screeninit code, Kernel11 only uses PDN_GPU_CNT.bit16 to power-off VRAM before going to sleep.
 +
 
 +
==PDN_LCD_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
This register seems to be unimplemented in released models, only to be used in Boot11, as PDN_GPU_CNT.bit16 also drives the LCD clock.
 +
 
 +
==PDN_FCRAM_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset.
 +
|-
 +
| 1
 +
| Clock. 1 = enable, 0 = disable
 +
|-
 +
| 2
 +
| Acknowledge clock request. Gets set or unset when toggling bit 1.
 +
|}
 +
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. AgbBg clears bit 0 in reg 0x10201000 before touching this reg.
 +
 
 +
Kernel11 uses it to put the FCRAM in self-refresh mode (clock disable) before going to sleep.
 +
 
 +
==PDN_I2S_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| I2S1 Clock (maybe?) 1 = enable, 0 = disable
 +
|-
 +
| 1
 +
| I2S2 Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
I2S1 clock enable bit seems to be unimplemented. Maybe it's because DSP clock enable drives it?
 +
 
 +
==PDN_CAMERA_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
==PDN_DSP_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset.
 +
|-
 +
| 1
 +
| Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
PDN services holds reset for 0x30 Arm11 cycles.
 +
 
 +
==PDN_MVD_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset
 +
|}
 +
 
 +
This doesn't seem to be used by anything, but does have a clear effect on the hardware.
 +
 
 +
The reset value for this register is 1 (out-of-reset at boot).
 +
 
 +
=N3DS SoC (LGR) registers=
 +
== PDN_LGR_SOCMODE ==
 +
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2
 +
| SoC mode.
 +
Possible values:
 +
  0=CTR+256MHz
 +
  1=LGR2+256MHz, 5=LGR2+804MHz
 +
  2=LGR1+256MHz, 3=LGR1+536MHz
 +
 
 +
N3DS modes (LGR1/LGR2) enable the New 3DS FCRAM extension and are needed to access N3DS-only devices.
 +
 
 +
* CTR: O3DS
 +
* LGR1: N3DS prototype, 4 cores (originally 2), no L2C
 +
* LGR2: retail N3DS, 4 cores, has L2C
 +
|-
 +
| 15
 +
| Interrupt status (read) / clear (write)
 +
|}
 +
 
 +
'''All currently powered-on cores must be (and remain) in WFI state to trigger the SoC mode switch.'''
 +
 
 +
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode.
 +
 
 +
On firmlaunch, the kernel sets the mode to O3DS.
 +
 
 +
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. This piece of code choses the mode matching the input Param0 bit0 state (1 for higher clock), using the state of [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] to determine which mode is the best (which is always LGR2 on all released New 3DS units).
 +
 
 +
== PDN_LGR_CNT ==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Enables the N3DS extramem block
 +
|-
 +
| 8
 +
| Enables the L2C block (LGR2 only)
 +
|}
 +
 
 +
Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] (LGR2 supported) is set otherwise 1.
 +
 
 +
== PDN_LGR_CPU_CNT<0-3> ==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Power request: 0 = power off, 1 = power on
 +
|-
 +
| 1
 +
| Handshake bit
 +
Needs to be set before powering on the core. It is meant to be cleared by software on the powered-on core, to signal itself.
 +
|-
 +
| 4
 +
| Power status: 0 = off, 1 = on
 +
|-
 +
| 5
 +
| Core present?
 +
|}
 +
 
 +
Only usable for core2 and core3. Core 0 and 1 have a fixed, read-only value of 0x30 for this register.
 +
 
 +
* On power-on, software should switch the affected core to Normal Mode on the SCU
 +
* On power-off, software '''must''' switch the affected core to Powered Off mode on the SCU (otherwise the core won't go off)
 +
 
 +
The normal Arm11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS Arm11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.
 +
 
 +
The overlay should be enabled by setting bit0 in [[CONFIG11_Registers#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]] and configured by setting the entrypoint address to [[CONFIG11_Registers#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].
 +
 
 +
The overlay overrides all ''instruction'' reads from phyiscal addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000 to the following (figured out by using low exception vectors and configuring the b11 veeners accordingly):
 +
  ldr pc, [pc, #(0x20 - 8)]
 +
 
 +
and all ''data'' reads from the same ranges to [[CONFIG11_Registers#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].
TuxSH
516

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