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PDN Registers (edit)

Revision as of 21:57, 1 June 2020

8,395 bytes added ,  21:57, 1 June 2020
PDN are their own registers. Also add a few of them
Line 1: Line 1: −
#REDIRECT [[CONFIG11 Registers]]
+
= Registers =
 +
{| class="wikitable" border="1"
 +
!  Old3DS
 +
!  Name
 +
!  Address
 +
!  Width
 +
!  Used by
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_CNT|PDN_CNT]]
 +
| 0x10141000
 +
| 2
 +
| Kernel11, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]]
 +
| 0x10141008
 +
| 4
 +
| [[PTM Services]], [[PDN Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_WAKE_REASON|PDN_WAKE_REASON]]
 +
| 0x1014100C
 +
| 4
 +
| [[PTM Services]], TwlBg, [[PDN Services]]
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 +
| [[#LGY_MODE|LGY_MODE]]
 +
| 0x10141100
 +
| 2
 +
| TwlProcess9, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_SLEEP|LGY_SLEEP]]
 +
| 0x10141104
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_IRQ_?|LGY_IRQ_?]]
 +
| 0x10141108
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#LGY_PADCNT|LGY_PADCNT]]
 +
| 0x1014110A
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_WIFIUNK|PDN_WIFI_UNK]]
 +
| 0x1014110C
 +
| 1
 +
| [[NWM Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_TWLAGB_HIDEMU_MASK|PDN_TWLAGB_HIDEMU_MASK]]
 +
| 0x10141110
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_TWLAGB_HIDEMU_PAD|PDN_TWLAGB_HIDEMU_PAD]]
 +
| 0x10141112
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_CODEC|PDN_CODEC_0]]
 +
| 0x10141114
 +
| 2
 +
| [[Codec Services]], TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_CODEC|PDN_CODEC_1]]
 +
| 0x10141116
 +
| 2
 +
| [[Codec Services]], TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| ?
 +
| 0x10141118
 +
| 1
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| ?
 +
| 0x10141119
 +
| 1
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| ?
 +
| 0x10141120
 +
| 1
 +
| TwlBg
 +
|-
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 +
| [[#PDN_GPU_CNT|PDN_GPU_CNT]]
 +
| 0x10141200
 +
| 4
 +
| Boot11, Kernel11, [[PDN Services]], TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_VRAM_CNT|PDN_VRAM_CNT]]
 +
| 0x10141204
 +
| 4
 +
| Boot11, Kernel11, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| PDN_FCRAM_CNT
 +
| 0x10141210
 +
| 2
 +
| Kernel11, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_CODEC_CNT|PDN_CODEC_CNT]]
 +
| 0x10141220
 +
| 1
 +
| Boot11, TwlBg, [[PDN Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_CAMERA_CNT|PDN_CAMERA_CNT]]
 +
| 0x10141224
 +
| 1
 +
| [[PDN Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_DSP_CNT|PDN_DSP_CNT]]
 +
| 0x10141230
 +
| 1
 +
| Process9, [[PDN Services]]
 +
|-style="border-top: double"
 +
| style="background: red" | No
 +
| [[#PDN_MPCORE_CLKCNT|PDN_MPCORE_CLKCNT]]
 +
| 0x10141300
 +
| 2
 +
| NewKernel11
 +
|-
 +
| style="background: red" | No
 +
| [[#PDN_MPCORE_CNT|PDN_MPCORE_CNT]]
 +
| 0x10141304
 +
| 2
 +
| NewKernel11
 +
|-
 +
| style="background: red" | No
 +
| [[#PDN_MPCORE_BOOTCNT<0-3>|PDN_MPCORE_BOOTCNT]]<0-3>
 +
| 0x10141310
 +
| 1*4
 +
| NewKernel11
 +
|}
 +
 
 +
==PDN_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| 1 = Enter sleep mode
 +
|-
 +
| 2-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = VRAM is in self-refresh mode
 +
|}
 +
 
 +
Kernel11 puts VRAM in self-refresh mode (before going to sleep) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally polls this register.
 +
 
 +
==PDN_WAKE_ENABLE==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 1
 +
| [[HID_Registers#HID_PADCNT|HID_PADCNT]]
 +
|-
 +
| 3
 +
| Shell opened
 +
|-
 +
| 4
 +
| Headphones not plugged in
 +
|-
 +
| 8
 +
| WiFi (?)
 +
|-
 +
| 19
 +
| Shell GPIO (?)
 +
|-
 +
| 26
 +
| [[I2C_Registers#Device_3|MCU interrupt]]
 +
|-
 +
| 30
 +
| Touch screen pressed
 +
|-
 +
| 31
 +
| CTR gamecard inserted/removed
 +
|-
 +
|}
 +
List in progress.
 +
 
 +
This is a OR list of wake triggers that will wake up the console from sleep and raise IRQ 0x58.
 +
 
 +
==PDN_WAKE_REASON==
 +
Same layout as [[#PDN_WAKE_ENABLE|PDN_WAKE_ENABLE]].
 +
 
 +
This is a OR list of the wake triggers that actually woke up the console.
 +
 
 +
For each bit, write 1 to acknowledge, read, then write 0 to clear.
 +
 
 +
==PDN_WIFICNT==
 +
{| class="wikitable" border="1"
 +
!  Old3DS
 +
!  Bits
 +
!  Description
 +
|-
 +
| style="background: green" | Yes
 +
| 0
 +
| Enable wifi subsystem
 +
|}
 +
 
 +
==LGY_MODE==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| Read only legacy mode set on reg 0x10018000.
 +
|-
 +
| 2-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = enable legacy mode.
 +
|}
 +
To boot into DSi or GBA mode first set register 0x10018000 to the desired mode and setup LgyFb. Then disable FCRAM by clearing bit 0 in reg 0x10201000, writing 0 to PDN_FCRAM_CNT followed by 1 and waiting for bit 2 to clear.
 +
 
 +
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.
 +
 
 +
==LGY_SLEEP==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Write 1 to wakeup GBA mode.
 +
|-
 +
| 1
 +
| Sleep state/ack. 1 when GBA mode entered sleep. Write 1 to ack.
 +
|-
 +
| 2
 +
| ?
 +
|-
 +
| 3-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = IRQ enable (IRQ 0x59)
 +
|}
 +
When a GBA game enters sleep mode and bit 15 is 1, IRQ 0x59 fires and bit 1 is set. Bit 1 must be acknowledged/written together with bit 0 otherwise GBA mode wakes up from sleep early sometimes.
 +
 
 +
==LGY_IRQ_?==
 +
Bitfield.
 +
 
 +
==LGY_PADCNT==
 +
Also named "KEYCNT" on certain other DS(i)/GBA documentations.
 +
The value of this register is copied to [[HID_Registers|HID_PADCNT]] when GBA mode enters sleep.
 +
 
 +
==PDN_WIFIUNK==
 +
{| class="wikitable" border="1"
 +
!  Old3DS
 +
!  Bits
 +
!  Description
 +
|-
 +
| style="background: green" | Yes
 +
| 4
 +
| Wifi-related? Set to 1 very early in NWM-module.
 +
|}
 +
 
 +
==PDN_TWLAGB_HIDEMU_MASK==
 +
Set bits will use the corresponding values from [[#PDN_TWLAGB_HIDEMU_PAD|PDN_TWLAGB_HIDEMU_PAD]] instead of allowing the hardware to read it from [[HID_Registers#HID_PAD|HID_PAD]].
 +
 
 +
This is set to 0x1FFF (all buttons and the debug key) and [[#PDN_TWLAGB_HIDEMU_PAD|PDN_TWLAGB_HIDEMU_PAD]] is set to 0 when the "Close this software and return to HOME Menu?" dialog is shown to prevent the button presses from propagating to the DS/GBA CPU.
 +
 
 +
==PDN_TWLAGB_HIDEMU_PAD==
 +
Works the same way as [[HID_Registers#HID_PAD|HID_PAD]], but the values set here are only replaced in the HID_PAD seen by the DS/GBA CPU when the corresponding bits in [[#PDN_TWLAGB_HIDEMU_MASK|PDN_TWLAGB_HIDEMU_MASK]] are set.
 +
 
 +
==PDN_GPU_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown reset. 0 = reset.
 +
|-
 +
| 1
 +
| PSC block reset? 0 = reset.
 +
|-
 +
| 2
 +
| Geoshader block reset? 0 = reset.
 +
|-
 +
| 3
 +
| Rasterization block reset? 0 = reset.
 +
|-
 +
| 4
 +
| PPF block reset. 0 = reset.
 +
|-
 +
| 5
 +
| PDC block reset? 0 = reset.
 +
|-
 +
| 6
 +
| PDC related reset. 0 = reset.
 +
|-
 +
| 7-15
 +
| Unused.
 +
|-
 +
| 16
 +
| Clock enable for all blocks. 1 = enable.
 +
|}
 +
Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled).
 +
When this is unset VRAM is not accessible and triggers exceptions.
 +
 
 +
PDN uses a 12 ARM11 cycle delay to deassert reset.
 +
 
 +
==PDN_VRAM_CNT==
 +
Bit0: Enable VRAM clock in older models??
 +
 
 +
This registers seems to be unimplemented in released models: while it is used in tandem with PDN_GPU_CNT.bit16 in boot11 screeninit code, Kernel11 only uses PDN_GPU_CNT.bit16 to put VRAM in self-refresh mode.
 +
 
 +
==PDN_FCRAM_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset.
 +
|-
 +
| 1
 +
| Clock. 1 = enable, 0 = disable
 +
|-
 +
| 2
 +
| Acknowledge clock request. Gets set or unset when toggling bit 1.
 +
|}
 +
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. Agb-/TwlBg clears bit 0 in reg 0x10201000 before touching this reg.
 +
 
 +
Kernel11 uses it before going to sleep. It does a dummy read before touching this reg.
 +
 
 +
==PDN_CODEC==
 +
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.
 +
 
 +
==PDN_CODEC_CNT==
 +
This is the power register used for the [[PDN_Services|PDN]] CODEC service.
 +
 
 +
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.
 +
 
 +
==PDN_CAMERA_CNT==
 +
This is the power register used for the [[PDN_Services|PDN]] camera service.
 +
 
 +
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
 +
 
 +
==PDN_DSP_CNT==
 +
This is the power register used for the [[PDN_Services|PDN Services]] DSP service.
 +
 
 +
bit0: NRESET (active low). Unset to reset/hold reset.
 +
bit1: enable bit.
 +
 
 +
PDN services holds reset for 0x30 Arm11 cycles.
TuxSH
516

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