516
edits
Changes
Jump to navigation
Jump to search
Line 429:
Line 429: − + Line 443:
Line 443: − + − {| class="wikitable" border="1" − ! Register value − ! Higher-clockrate bit set in svcKernelSetState Param0 − ! CFG11_SOCINFO bit2 set − ! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state − ! Clock-rate multiplier − ! Description − |- − | 0x01 − | No − | Yes − | 0x01 − | 1x − | 268MHz − |- − | 0x02 − | No − | No − | 0x01 − | 1x − | 268MHz − |- − | 0x05 − | Yes − | Yes − | 0x03 − | 3x − | 804MHz − |- − | 0x03 − | Yes − | No − | 0x02 − | 2x − | 536MHz (tested on New3DS) − |} − − Note that the above CFG11_SOCINFO bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). − − The following register value(s) were tested on New3DS by patching the kernel: − * 0x00: Entire system hangs. − * 0x02: Entire system hangs. − * 0x03: ARM11 runs at 536MHz. − * 0x04: Entire system hangs. − * 0x06: Entire system hangs. − * 0x07: Same result as 0x05. − * 0x08: Entire system hangs. − * 0x09: Entire system hangs. − * 0x0A: Entire system hangs. − * 0x0B: Same result as 0x03. − * 0x0C: Entire system hangs. − * 0x0D: Same result as 0x05. − * 0x0E: Entire system hangs. − * 0x0F: Same result as 0x05. − * 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
Cleanup →PDN_LGR_SOCMODE
0=CTR+256MHz
0=CTR+256MHz
1=LGR2+256MHz, 5=LGR2+804MHz
1=LGR2+256MHz, 5=LGR2+804MHz
2=LGR+256MHz, 3=LGR+536MHz
2=LGR1+256MHz, 3=LGR1+536MHz
N3DS modes (LGR1/LGR2) enable the New 3DS FCRAM extension and are needed to access N3DS-only devices.
N3DS modes (LGR1/LGR2) enable the New 3DS FCRAM extension and are needed to access N3DS-only devices.
On firmlaunch, the kernel sets the mode to O3DS.
On firmlaunch, the kernel sets the mode to O3DS.
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]]:
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. This piece of code choses the mode matching the input Param0 bit0 state (1 for higher clock), using the state of [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] to determine which mode is the best (which is always LGR2 on all released New 3DS units).
== PDN_LGR_CNT ==
== PDN_LGR_CNT ==