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597 bytes added ,  01:34, 6 February 2021
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= Overview =
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The RSA module is essentially a hardware-accelerated modular exponentiation engine. It is specially optimized for RSA applications, so its behavior can be incoherent when RSA's invariants are broken.
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=== Observed edge cases ===
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* if 2 divides mod, output == 0
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= Registers =
 
= Registers =
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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| [[#RSA_EXPFIFO|RSA_EXPFIFO]]
 
| [[#RSA_EXPFIFO|RSA_EXPFIFO]]
 
| 0x1000B200
 
| 0x1000B200
| 0x04
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| 0x100 (can handle u32 writes to any aligned position in the FIFO)
 
|
 
|
 
|-
 
|-
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|-
 
|-
 
| 1
 
| 1
| ?
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| Interrupt enable (1=enable, 0=disable)
 
|-
 
|-
 
| 4-7
 
| 4-7
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|-
 
|-
 
| 8
 
| 8
| Endianness (1=Little endian, 0=Big endian)
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| Endianness (1=Little endian, 0=Big endian). Affects RSA_EXPFIFO, RSA_MOD, and RSA_TXT.
 
|-
 
|-
 
| 9
 
| 9
| Word order (1=Normal order, 0=Reversed order)
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| Word order (1=Normal order, 0=Reversed order). Affects RSA_MOD and RSA_TXT.
 
|}
 
|}
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| Key write-protect, this bit is RW. (0 = no protection, 1 = protected)
 
| Key write-protect, this bit is RW. (0 = no protection, 1 = protected)
 
|-
 
|-
| 30-2
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| 2
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| Key read-protect, this bit is RW. (0 = no protection, 1 = protected)
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|-
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| 30-3
 
| ?
 
| ?
 
|-
 
|-
 
| 31
 
| 31
| ?
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| Key slot protect. Makes all other bits in this reg read-only until reset
 
|}
 
|}
  
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