Difference between revisions of "SHA Registers"
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| − | + | = Registers = | |
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
| − | ! | + | ! Old3DS |
| − | ! | + | ! Name |
| − | ! | + | ! Address |
| + | ! Width | ||
| + | ! Used by | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_CNT|SHA_CNT]] | ||
| 0x1000A000 | | 0x1000A000 | ||
| 4 | | 4 | ||
| + | | Boot9, Process9 | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_BLKCNT|SHA_BLKCNT]] | ||
| 0x1000A004 | | 0x1000A004 | ||
| 4 | | 4 | ||
| + | | Process9 | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_HASH|SHA_HASH]] | ||
| 0x1000A040 | | 0x1000A040 | ||
| 0x20 | | 0x20 | ||
| + | | Process9 | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_FIFO|SHA_FIFO]] | ||
| 0x1000A080 | | 0x1000A080 | ||
| 0x40 | | 0x40 | ||
| + | | Boot9, Process9 | ||
|} | |} | ||
| − | + | == SHA_CNT == | |
| − | == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
! Description | ! Description | ||
|- | |- | ||
| − | | 0-1 | + | | 0 |
| − | | 0= | + | | Start (1=enable/busy, 0=idle) |
| + | |- | ||
| + | | 1 | ||
| + | | Final round (1=enable/busy, 0=normal) | ||
| + | |- | ||
| + | | 2 | ||
| + | | Enable IRQ 0 | ||
| + | |- | ||
| + | | 3 | ||
| + | | Output Endianess (0=little, 1=big) | ||
| + | |- | ||
| + | | 4-5 | ||
| + | | Mode (0=SHA256, 1=SHA224, 2=3=SHA1) | ||
| + | |- | ||
| + | | 6 | ||
| + | | ? | ||
| + | |- | ||
| + | | 7 | ||
| + | | ? | ||
| + | |- | ||
| + | | 8 | ||
| + | | Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO. | ||
| + | |- | ||
| + | | 9 | ||
| + | | Enable FIFO (1=fifo, 0=write-only) | ||
|- | |- | ||
| − | | | + | | 10 |
| − | | | + | | Enable IRQ 1 |
|- | |- | ||
| 16 | | 16 | ||
| − | | | + | | ? |
|- | |- | ||
| 17 | | 17 | ||
| − | | | + | | ? |
|} | |} | ||
| + | == SHA_BLKCNT == | ||
| + | This reg contains the total size of the data written to REG_SHA_IN, this field is updated when performing hash-function final-round. | ||
| − | == | + | == SHA_HASH == |
| − | This reg contains the | + | This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register. |
| − | == | + | == SHA_FIFO == |
| − | + | The data to be hashed must be written here. It does not matter what offset is written to. | |
Revision as of 04:03, 6 January 2017
Registers
| Old3DS | Name | Address | Width | Used by |
|---|---|---|---|---|
| Yes | SHA_CNT | 0x1000A000 | 4 | Boot9, Process9 |
| Yes | SHA_BLKCNT | 0x1000A004 | 4 | Process9 |
| Yes | SHA_HASH | 0x1000A040 | 0x20 | Process9 |
| Yes | SHA_FIFO | 0x1000A080 | 0x40 | Boot9, Process9 |
SHA_CNT
| Bits | Description |
|---|---|
| 0 | Start (1=enable/busy, 0=idle) |
| 1 | Final round (1=enable/busy, 0=normal) |
| 2 | Enable IRQ 0 |
| 3 | Output Endianess (0=little, 1=big) |
| 4-5 | Mode (0=SHA256, 1=SHA224, 2=3=SHA1) |
| 6 | ? |
| 7 | ? |
| 8 | Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO. |
| 9 | Enable FIFO (1=fifo, 0=write-only) |
| 10 | Enable IRQ 1 |
| 16 | ? |
| 17 | ? |
SHA_BLKCNT
This reg contains the total size of the data written to REG_SHA_IN, this field is updated when performing hash-function final-round.
SHA_HASH
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.
SHA_FIFO
The data to be hashed must be written here. It does not matter what offset is written to.