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SPI Registers (edit)

Revision as of 21:54, 20 April 2019

60 bytes added ,  21:54, 20 April 2019
m
→‎SPI_NEW_STATUS
Line 231: Line 231:     
==SPI_NEW_STATUS==
 
==SPI_NEW_STATUS==
−
Bit0: FIFO busy.
+
Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.
Profi200
136

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