136
edits
Changes
→Registers: Use same naming scheme as NDMA
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]0
| [[#NSPI_CNT|NSPI_CNT]]0
| 0x10142800
| 0x10142800
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]0
| [[#NSPI_DONE|NSPI_DONE]]0
| 0x10142804
| 0x10142804
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]0
| [[#NSPI_BLKLEN|NSPI_BLKLEN]]0
| 0x10142808
| 0x10142808
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]0
| [[#NSPI_FIFO|NSPI_FIFO]]0
| 0x1014280C
| 0x1014280C
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]0
| [[#NSPI_STATUS|NSPI_STATUS]]0
| 0x10142810
| 0x10142810
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]1
| [[#NSPI_CNT|NSPI_CNT]]1
| 0x10143800
| 0x10143800
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]1
| [[#NSPI_DONE|NSPI_DONE]]1
| 0x10143804
| 0x10143804
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]1
| [[#NSPI_BLKLEN|NSPI_BLKLEN]]1
| 0x10143808
| 0x10143808
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]1
| [[#NSPI_FIFO|NSPI_FIFO]]1
| 0x1014380C
| 0x1014380C
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]1
| [[#NSPI_STATUS|NSPI_STATUS]]1
| 0x10143810
| 0x10143810
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]2
| [[#NSPI_CNT|NSPI_CNT]]2
| 0x10160800
| 0x10160800
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]2
| [[#NSPI_DONE|NSPI_DONE]]2
| 0x10160804
| 0x10160804
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]2
| [[#NSPI_BLKLEN|NSPI_BLKLEN]]2
| 0x10160808
| 0x10160808
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]2
| [[#NSPI_FIFO|NSPI_FIFO]]2
| 0x1016080C
| 0x1016080C
| 4
| 4
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]2
| [[#NSPI_STATUS|NSPI_STATUS]]2
| 0x10160810
| 0x10160810
| 4
| 4
|}
|}
== SPI_NEW_CNT ==
== NSPI_CNT ==
This is an alternative faster interface introduced with the 3DS.
This is an alternative faster interface introduced with the 3DS.
|}
|}
== SPI_NEW_DONE ==
== NSPI_DONE ==
This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probaly the Chip Select line.
This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probably the Chip Select line.
==SPI_NEW_BLKLEN==
==NSPI_BLKLEN==
The number of bytes to be sent/read is written to this register.
The number of bytes to be sent/read is written to this register.
==SPI_NEW_FIFO==
==NSPI_FIFO==
32-bit FIFO for reading/writing the SPI payload.
32-bit FIFO for reading/writing the SPI payload.
==SPI_NEW_STATUS==
==NSPI_STATUS==
Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.
Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.