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Line 7,578: − + − + − + − + − This register is used to set the geometry shader's i0 integer register.+ − + Line 7,598:
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Line 7,619: − + − + − | 8-15+ − | unsigned, Value for geometry shader's i2.y+ − |- − − | unsigned, Value for geometry shader's i2.z − |- − | 24-31 − | unsigned, Value for geometry shader's i2.w − |} − − This register is used to set the geometry shader's i2 integer register. − − === GPUREG_GSH_INTUNIFORM_I3 === − − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0-7 − | unsigned, Value for geometry shader's i3.x − |- − | 8-15 − | unsigned, Value for geometry shader's i3.y − |- − | 16-23 − | unsigned, Value for geometry shader's i3.z − |- − | 24-31 − | unsigned, Value for geometry shader's i3.w − |} − − This register is used to set the geometry shader's i3 integer register. − − === GPUREG_GSH_INPUTBUFFER_CONFIG === − − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0-7 − | unsigned, Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register) − |- − | 8-23 − | Unknown. These bits typically aren't updated by games. − |- − | 24-31 − − + + − === GPUREG_GSH_ENTRYPOINT ===+ − − {| class="wikitable" border="1" − ! Bits − ! Description − |- − | 0-15 − | unsigned, Geometry shader unit entrypoint, in words. − |- − | 16-31 − | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang − |} − − This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader. − + Line 7,696:
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Line 7,810: − + − + − − NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095. − + Line 7,853:
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→Shader registers
|}
|}
== Geometry shader registers ==
== Shader registers ==
=== GPUREG_GSH_BOOLUNIFORM ===
=== GPUREG_''SH''_BOOLUNIFORM ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| unsigned, Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
|-
| 1
| 1
| unsigned, Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
|-
| 2
| 2
| unsigned, Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
|-
| 3
| 3
| unsigned, Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
|-
| 4
| 4
| unsigned, Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
|-
| 5
| 5
| unsigned, Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
|-
| 6
| 6
| unsigned, Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
|-
| 7
| 7
| unsigned, Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
|-
| 8
| 8
| unsigned, Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
|-
| 9
| 9
| unsigned, Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
|-
| 10
| 10
| unsigned, Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
|-
| 11
| 11
| unsigned, Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
|-
| 12
| 12
| unsigned, Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
|-
| 13
| 13
| unsigned, Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
|-
| 14
| 14
| unsigned, Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
|-
| 15
| 15
| unsigned, Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
|-
| 16-31
| 16-31
| Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang
| 0x7FFF
|}
|}
This register is used to set the geometry shader unit's boolean registers.
This register is used to set a shader unit's boolean registers.
=== GPUREG_GSH_INTUNIFORM_I0 ===
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-7
| 0-7
| unsigned, Value for geometry shader's i0.x
| unsigned, Integer register i''i'' X value
|-
|-
| 8-15
| 8-15
| unsigned, Value for geometry shader's i0.y
| unsigned, Integer register i''i'' Y value
|-
|-
| 16-23
| 16-23
| unsigned, Value for geometry shader's i0.z
| unsigned, Integer register i''i'' Z value
|-
|-
| 24-31
| 24-31
| unsigned, Value for geometry shader's i0.w
| unsigned, Integer register i''i'' W value
|}
|}
These registers are used to set a shader unit's integer registers.
=== GPUREG_GSH_INTUNIFORM_I1 ===
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-3
| unsigned, Value for geometry shader's i1.x
| unsigned, Input vertex attributes - 1
|-
|-
| 8-15
| 8-15
| unsigned, Value for geometry shader's i1.y
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
|-
| 16-23
| 16-23
| unsigned, Value for geometry shader's i1.z
| 0x0
|-
|-
| 24-31
| 24-31
| unsigned, Value for geometry shader's i1.w
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}
|}
This register is used to set the geometry shader's i1 integer register.
This register is used to configure a shader unit's input buffer.
=== GPUREG_GSH_INTUNIFORM_I2 ===
=== GPUREG_''SH''_ENTRYPOINT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-7
| 0-15
| unsigned, Value for geometry shader's i2.x
| unsigned, Code entry point offset, in 32-bit words
|-
|-
| 16-31
| 0x7FFF
| 16-23
| Unknown. This is typically set to 8 for geometry shaders.
|}
|}
This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.
This register sets a shader unit's code entry point.
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-3
| 0-3
| unsigned, Index of geometry shader input register which the 1st attribute will be stored in.
| unsigned, Vertex attribute 0 input register index
|-
|-
| 4-7
| 4-7
| unsigned, Index of geometry shader input register which the 2nd attribute will be stored in.
| unsigned, Vertex attribute 1 input register index
|-
|-
| 8-11
| 8-11
| unsigned, Index of geometry shader input register which the 3rd attribute will be stored in.
| unsigned, Vertex attribute 2 input register index
|-
|-
| 12-15
| 12-15
| unsigned, Index of geometry shader input register which the 4th attribute will be stored in.
| unsigned, Vertex attribute 3 input register index
|-
|-
| 16-19
| 16-19
| unsigned, Index of geometry shader input register which the 5th attribute will be stored in.
| unsigned, Vertex attribute 4 input register index
|-
|-
| 20-23
| 20-23
| unsigned, Index of geometry shader input register which the 6th attribute will be stored in.
| unsigned, Vertex attribute 5 input register index
|-
|-
| 24-27
| 24-27
| unsigned, Index of geometry shader input register which the 7th attribute will be stored in.
| unsigned, Vertex attribute 6 input register index
|-
|-
| 28-31
| 28-31
| unsigned, Index of geometry shader input register which the 8th attribute will be stored in.
| unsigned, Vertex attribute 7 input register index
|}
|}
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-3
| 0-3
| unsigned, Index of geometry shader input register which the 9th attribute will be stored in.
| unsigned, Vertex attribute 8 input register index
|-
|-
| 4-7
| 4-7
| unsigned, Index of geometry shader input register which the 10th attribute will be stored in.
| unsigned, Vertex attribute 9 input register index
|-
|-
| 8-11
| 8-11
| unsigned, Index of geometry shader input register which the 11th attribute will be stored in.
| unsigned, Vertex attribute 10 input register index
|-
|-
| 12-15
| 12-15
| unsigned, Index of geometry shader input register which the 12th attribute will be stored in.
| unsigned, Vertex attribute 11 input register index
|-
|-
| 16-19
| 16-19
| unsigned, Index of geometry shader input register which the 13th attribute will be stored in.
| unsigned, Vertex attribute 12 input register index
|-
|-
| 20-23
| 20-23
| unsigned, Index of geometry shader input register which the 14th attribute will be stored in.
| unsigned, Vertex attribute 13 input register index
|-
|-
| 24-27
| 24-27
| unsigned, Index of geometry shader input register which the 15th attribute will be stored in.
| unsigned, Vertex attribute 14 input register index
|-
|-
| 28-31
| 28-31
| unsigned, Index of geometry shader input register which the 16th attribute will be stored in.
| unsigned, Vertex attribute 15 input register index
|}
|}
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
=== GPUREG_GSH_OUTMAP_MASK ===
=== GPUREG_''SH''_OUTMAP_MASK ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| unsigned, Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
|-
| 1
| 1
| unsigned, Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
|-
| 2
| 2
| unsigned, Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
|-
| 3
| 3
| unsigned, Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
|-
| 4
| 4
| unsigned, Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
|-
| 5
| 5
| unsigned, Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
|-
| 6
| 6
| unsigned, Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}
|}
This register toggles the geometry shader unit's output registers.
This register toggles a shader unit's output registers.
=== GPUREG_GSH_CODETRANSFER_END ===
=== GPUREG_''SH''_CODETRANSFER_END ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0
| 0-31
| unsigned, Code data transfer end signal bit.
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}
|}
This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
This register's value should be set to 1 in order to finalize the transfer of shader code.
=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-6
| 0-7
| unsigned, Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
|-
| 31
| 31
| unsigned, Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}
|}
This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.
=== GPUREG_GSH_FLOATUNIFORM_DATA ===
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
| Floating-point register component data
|}
|}
This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** second word : YYYYZZZZ
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
=== GPUREG_GSH_CODETRANSFER_CONFIG ===
=== GPUREG_''SH''_CODETRANSFER_INDEX ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-11
| 0-11
| unsigned, Target geometry shader code offset for data transfer.
| unsigned, Target shader code offset
|}
|}
This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.
=== GPUREG_GSH_CODETRANSFER_DATA ===
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| unsigned, Geometry shader instruction data.
| unsigned, Shader instruction data
|}
|}
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.
=== GPUREG_GSH_OPDESCS_CONFIG ===
=== GPUREG_''SH''_OPDESCS_INDEX ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Description
! Description
|-
|-
| 0-6
| 0-11
| unsigned, Target geometry shader operand descriptor offset for data transfer.
| unsigned, Target shader operand descriptor offset
|}
|}
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.
=== GPUREG_GSH_OPDESCS_DATA ===
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0-31
| 0-31
| unsigned, Geometry shader operand descriptor data.
| unsigned, Shader operand descriptor data
|}
|}
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.
== Vertex shader registers ==
== Vertex shader registers ==