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− | == Registers ==
| + | = Registers = |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
− | ! NAME | + | ! Old3DS |
− | ! ADDRESS | + | ! Name |
− | ! WIDTH | + | ! Address |
| + | ! Width |
| + | ! Used by |
| |- | | |- |
− | | REG_PXISYNC | + | | style="background: green" | Yes |
− | | 0x1EC63000 | + | | [[#PXI_SYNC|PXI_SYNC]]9 |
| + | | 0x10008000 |
| | 4 | | | 4 |
| + | | Boot9, Process9 |
| |- | | |- |
− | | REG_PXICNT | + | | style="background: green" | Yes |
− | | 0x1EC63004 | + | | [[#PXI_CNT|PXI_CNT]]9 |
| + | | 0x10008004 |
| + | | 2 |
| + | | Boot9, Process9 |
| + | |- |
| + | | style="background: green" | Yes |
| + | | PXI_SEND9 |
| + | | 0x10008008 |
| | 4 | | | 4 |
| + | | |
| |- | | |- |
− | | REG_PXISEND | + | | style="background: green" | Yes |
− | | 0x1EC63008 | + | | PXI_RECV9 |
| + | | 0x1000800C |
| + | | 4 |
| + | | |
| + | |-style="border-top: double" |
| + | | style="background: green" | Yes |
| + | | [[#PXI_SYNC|PXI_SYNC]]11 |
| + | | 0x10163000 |
| | 4 | | | 4 |
| + | | Boot11 |
| + | |- |
| + | | style="background: green" | Yes |
| + | | [[#PXI_CNT|PXI_CNT]]11 |
| + | | 0x10163004 |
| + | | 2 |
| + | | Boot11 |
| |- | | |- |
− | | REG_PXIRECV | + | | style="background: green" | Yes |
− | | 0x1EC6300C | + | | PXI_SEND11 |
| + | | 0x10163008 |
| | 4 | | | 4 |
| + | | |
| + | |- |
| + | | style="background: green" | Yes |
| + | | PXI_RECV11 |
| + | | 0x1016300C |
| + | | 4 |
| + | | |
| |} | | |} |
| | | |
− | The PXI registers are exactly the same as on DS. | + | The PXI registers are similar to those on DS. |
| + | |
| + | == PXI_SYNC == |
| + | {| class="wikitable" border="1" |
| + | ! Bit |
| + | ! RW |
| + | ! Description |
| + | |- |
| + | | 0-7 |
| + | | R |
| + | | Data received from remote bits 8-15 (unrelated to SEND/RECV FIFOs) |
| + | |- |
| + | | 8-15 |
| + | | R/W |
| + | | Data sent to remote bits 0-7 |
| + | |- |
| + | | 23 |
| + | | ? |
| + | | ? |
| + | |- |
| + | | 29 |
| + | | W? |
| + | | Trigger PXI_SYNC11 IRQ (if enabled) |
| + | |- |
| + | | 30 |
| + | | W? |
| + | | Trigger PXI_SYNC9 IRQ (if enabled) |
| + | |- |
| + | | 31 |
| + | | RW |
| + | | PXI_SYNC IRQ enable (for local processor) |
| + | |} |
| + | |
| + | This can also be accessed as 4 u8 registers. |
| + | |
| + | == PXI_CNT == |
| + | {| class="wikitable" border="1" |
| + | ! Bit |
| + | ! RW |
| + | ! Description |
| + | |- |
| + | | 0 |
| + | | R |
| + | | Send Fifo Empty Status (0=Not Empty, 1=Empty) |
| + | |- |
| + | | 1 |
| + | | R |
| + | | Send Fifo Full Status (0=Not Full, 1=Full) |
| + | |- |
| + | | 2 |
| + | | R/W |
| + | | Send Fifo Empty IRQ (0=Disable, 1=Enable) |
| + | |- |
| + | | 3 |
| + | | W |
| + | | Send Fifo Clear (0=Nothing, 1=Flush Send Fifo) |
| + | |- |
| + | | 8 |
| + | | R |
| + | | Receive Fifo Empty (0=Not Empty, 1=Empty) |
| + | |- |
| + | | 9 |
| + | | R |
| + | | Receive Fifo Full (0=Not Full, 1=Full) |
| + | |- |
| + | | 10 |
| + | | R/W |
| + | | Receive Fifo Not Empty IRQ (0=Disable, 1=Enable) |
| + | |- |
| + | | 14 |
| + | | R/W |
| + | | Error, Read Empty/Send Full (0=No Error, 1=Error/Acknowledge) |
| + | |- |
| + | | 15 |
| + | | R/W |
| + | | Enable Send/Receive Fifo (0=Disable, 1=Enable) |
| + | |} |