GPU/External Registers: Difference between revisions
→0x1EF00C10: Clarify display transfer line crop bit |
→Transfer Engine: Added TextureCopy documentation |
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|- | |- | ||
| 0x1EF00C00 | | 0x1EF00C00 | ||
| Input physical address>>3 | | Input physical address >> 3 | ||
|- | |- | ||
| 0x1EF00C04 | | 0x1EF00C04 | ||
| Output physical address>>3 | | Output physical address >> 3 | ||
|- | |- | ||
| 0x1EF00C08 | | 0x1EF00C08 | ||
| | | DisplayTransfer output width (bits 0-15) and height (bits 16-31). | ||
|- | |- | ||
| 0x1EF00C0C | | 0x1EF00C0C | ||
| | | DisplayTransfer input width and height. | ||
|- | |- | ||
| 0x1EF00C10 | | 0x1EF00C10 | ||
| | | Transfer flags. (See below) | ||
|- | |- | ||
| 0x1EF00C14 | | 0x1EF00C14 | ||
Line 259: | Line 259: | ||
|- | |- | ||
| 0x1EF00C20 | | 0x1EF00C20 | ||
| | | TextureCopy total amount of data to copy, in bytes. | ||
|- | |- | ||
| 0x1EF00C24 | | 0x1EF00C24 | ||
| | | TextureCopy input line width (bits 0-15) and gap (bits 16-31), in bytes. | ||
|- | |- | ||
| 0x1EF00C28 | | 0x1EF00C28 | ||
| | | TextureCopy output line width and gap. | ||
|} | |} | ||
These registers are used by [[GSP_Shared_Memory|GX command]] 3 and 4. For cmd4, *0x1EF00C18 |= 1 is used instead of just writing value 1 | These registers are used by [[GSP_Shared_Memory|GX command]] 3 and 4. For cmd4, *0x1EF00C18 |= 1 is used instead of just writing value 1. | ||
==== 0x1EF00C10 ==== | ==== Flags Register - 0x1EF00C10 ==== | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bit | ! Bit | ||
Line 285: | Line 285: | ||
|- | |- | ||
| 3 | | 3 | ||
| Uses a TextureCopy mode transfer. | | Uses a TextureCopy mode transfer. See below for details. | ||
|- | |- | ||
| 4 | | 4 | ||
Line 320: | Line 320: | ||
| Not writable | | Not writable | ||
|} | |} | ||
=== TextureCopy === | |||
When bit 3 of the control register is set, the hardware performs a TextureCopy-mode transfer. In this mode, all other bits of the control register (except for bit 2, which still needs to be set correctly) and the regular dimension registers are ignored, and no format conversions are done. Instead, it performs a raw data copy from the source to the destination, but with a configurable gap between lines. The total amount of bytes to copy is specified in the size register, and the hardware loops reading lines from the input and writing them to the output until this amount is copied. The "gap" specified in the input/output dimension register is the number of bytes to skip after each "width" bytes of the input/output, and is NOT counted towards the total size of the transfer. | |||
By correctly calculating the input and output gap sizes it is possible to use this functionality to copy arbitrary sub-rectangles between differently-sized framebuffers or textures, which is one of its main uses over a regular no-conversion DisplayTransfer. When copying tiled textures/framebuffers it's important to remember that the contents of a tile are laid out sequentially in memory, and so this should be taken into account when calculating the transfer parameters. | |||
== Command List == | == Command List == |